R.T.H. Rongen

Lifetime prediction of Cu-Al wire bonded contacts for different mould compounds

Large scale conversion of gold to copper wiring in microelectronics can only become successful when all the failure mechanisms that can be encountered during reliability testing, or during product application life are understood. One of these mechanisms is corrosion of the contact between the copper (Cu) ball and the aluminum (Al) bond-pad, consisting of various intermetallic compounds (IMCs), which are more sensitive to corrosion compared to gold (Au) Al IMC. This study elaborates on three corrosion mechanisms present in the Cu-Al system: interfacial Cu-Al IMC corrosion, bulk Cu-Al IMC corrosion and Al bond pad corrosion. For the first mechanism, which is dominant, an empirical corrosion model is introduced. To gather data for this model, a recently developed method for analyzing the IMC contact area to study the dynamics of the dominant mechanism is used. Data was collected from various devices, which were exposed to accelerated aging conditions. The focus of this paper is on unbiased conditions using a wide temperature and humidity range. In total four epoxy molding compound types have been investigated and are compared to each other, using the empirical model proposed in this paper. Finally, it is shown that the model allows the prediction of the life time of Cu-Al ball contacts for different application conditions and also allows the selection of an appropriate mould compound type.

Model and design rules for eliminating surface potential induced failures in high voltage integrated circuits

Abstract In HV integrated circuits. HV surface potentials originating from HV devices can induce parasitic leakage currents in low voltage circuitry causing circuit malfunctioning (‘charge-creep’). The evolution of these potentials as a function of time and place can be modelled by a lumped element RC network. The model predictions are in good agreement with experimental results and can be used to derive design rules for the minimum d safe to the HV-bondpad that is needed in order ensure that no ‘charge-creep’ effects will occur. All devices located closer to the HV-bondpad than d safe dr should be protected by proper shielding measures like e.g. field plates.

Degradation of Cu-Al wire bonded contacts under high current and high temperature conditions using in-situ resistance monitoring

To evaluate the dynamics of Cu-Al bond contact degradation, the evolution of the intermetallic electrical interface resistance was monitored in-situ in a test device exposed to high temperatures (140 to 200°C) while conducting high current densities (7.0 × 103 to 4.5 × 104 A/cm2). The degradation is quite different from what is known for Au-Al contacts. The influence of different stimuli like current direction, current density, temperature, and temperature gradients is studied and discussed. On top of that the dynamics in relation to material properties is assessed in detail from which the concept of an incubation time until IMC degradation starts is proposed.

Comparison of in-situ measurement techniques of solder joint reliability under thermo-mechanical stresses

Thermo Mechanical Cycle Lifetime (TMCL) test is a widely used test methodology for evaluating the reliability of solder joints in the microelectronics industry. The commonly used measurement techniques to monitor solder joint failures during the TMCL test are either event detector or data logger. In this study, TMCL test has been carried out on the same devices in parallel with both measurement techniques. The pros and cons of both techniques are compared. It is observed that the solder joint reliability results on the investigated samples by both techniques are comparable. The event detector can catch short intermittent events, while the data logger is able to capture the details of the solder joint degradation process. In applications for which performance is dependent on the transmission of signals with a frequency of several hundred megahertz or more, the event detector technique shall be used. In such cases the data logger technique may overestimate product lifetime. On the other hand, for some applications where the performance is less susceptible to intermittent solder joint interconnect interruption but more to the increase of the solder joint resistance, the data logger shall be used. In such cases the event detector technique may underestimate product lifetime. In conclusion depending on the end application of the device, the most suitable technique can be selected.

Electrical characterization of plastic encapsulations using an alternative gate leakage test method

The supply current of plastic encapsulated microelectronic devices in the presence of a high potential source can increase abnormally due to parasitic gate leakage. According to reliability qualification standards, stress during a parasitic gate leakage test is applied by a corona discharge at a thin tungsten needle placed a few centimeters above the devices under test. The gate leakage sensitivity factor obtained from this test lacks any physical basis and is therefore not believed to be useful. Here we show that this sensitivity factor can be replaced by a physical model for charge transport through the encapsulation material. The model is used to explain why devices encapsulated by a molding compound with a low volume resistivity of 6 times 1011 Ohm-cm, at high temperature, 150degC, are more prone to fail the test on an increased current, compared to devices encapsulated by a compound having a high resistivity of 4 times 1013 Ohmtimescm at the same temperature. Furthermore, we discuss an alternative test setup where the potential difference between two parallel electrodes sandwiching the devices is used as the source of stress. It is suggested in literature that this setup yields identical results as the current setup. However, using both setups on the same product did not result in an equal outcome, which indicates that both tests do not trigger the same failure mechanism to the same extent.

Copper wire interconnect reliability evaluation using in-situ High Temperature Storage Life (HTSL) tests

Abstract This paper describes the use of in-situ High Temperature Storage Life (HTSL) tests based on a four point resistance method to evaluate Cu wire interconnect reliability. Although the same set up was used in the past to monitor Au–Al ball bond degradation, a different approach was needed for this system. Using conventional statistical methods of failure probability distributions and a fixed failure criterion were found to be unsuitable in this case. Besides this, tests usually take very long until a sufficient percentage of the population have failed according to that criterion. A simple physical model was used to electrically quantify ball bond degradation due to the prevailing failure mechanism in a substantially smaller amount of test time. The method enabled the determination of activation energies for a number of moulding compounds and is extremely useful for a fast screening of such materials regarding their suitability for Cu wire.

Reliability of Wafer Level Chip Scale Packages

Abstract This paper describes applied reliability for semiconductor components in Wafer Level Chip Scale Packages (CSP). To develop and qualify reliable products, the failure mechanism driven approach is to be followed instead of the stress test driven one. This will be explained by elaborating on two failure mode cases assessed in WL-CSP: cracks in the passivation layer and top metal of the die/silicon and electromigration in the solder joints. A new TMCL test method is described that covers the direct (thermo) mechanical interaction between PCB and the die/design via the solder joint. In addition, the relevance of Finite Element Modeling to understand the origin of failure modes is shown which allows for optimizing designs and materials. Finally, the concept of life time prediction, starting from application use descriptions and mission profiles, is introduced. Reliability testing, modeling and life time prediction/reliability statistics are combined in one framework to accommodate for the creation of application specific, highly reliable components.

Effect of Environmental and Testing Conditions on Board Level Vibration

In this paper, the factors affecting the stability of the board level vibration testing are investigated by means of experimental testing combined with simulations. Environmental conditions and test parameters may affect the dynamic response of the PCB and thus the stress on the product. As the goal of the test is to predict solder joint reliability, the translation from test of surface mounted products on PCBs and field life once build in the final application unit becomes difficult. The natural frequency and the peak-to-peak displacement of the PCB are evaluated with an accelerometer, which is shown to have a similar impact on the dynamic behavior as large BGA packages. The influence of the PCB stack-up is also highlighted. Then, the temperature is varied between 17°C and 47°C, and the relative humidity between 30% and 60%. The temperature is shown to have a large impact on the displacement and the frequency, while the humidity is confirmed to have no influence. Next, increasing the acceleration from 1G to 10G is shown to increase the stress on the component and can potentially lead to faster test results. Nevertheless, it is observed to have a negative impact on the test stability since the frequency and displacement of the PCB are shifting during the test and the board is permanently damaged. The cables, used for the in-situ monitoring of daisy chains during the test in order to capture the intermittent contacts during the bending of the board, are shown to have an influence on the natural frequencies of the board, but predominantly on the higher order resonances. With the fixed environmental conditions and test parameters, a BGA package is tested and the failure distribution as well as the different failure modes observed are reported and discussed.

Simulation and measurement of the flip chip solder bumps with a Cu-plated plastic core

Abstract With the aim to miniaturize and to reduce the cost, the increasing demand, regarding to advanced 3D-packages as well as high performance applications, accelerates the development of 3D-silicon integrated circuits. The trend to smaller and lighter electronics has highlighted many efforts towards size reduction and increased performance in electronic products. The radio frequency (RF) performances are limited by parasitic effects due to the resistor–inductor–capacitor (RLC) network, between the wire bond connections from the dies to the lead frame. The use of flip-chip bonding technology for very fine pitch packaging allows high integration and limits parasitic inductances. Electromigration (EM) and thermomigration (TM) may have serious reliability issues for fine-pitch Pb-free solder bumps in the flip-chip technology used in consumer electronic products. A possibility to extend the reliability is the use of plastic ball in the solder bumps. Bumps containing a plastic solder balls have an excellent reliability. Using a plastic ball with a low Young modulus, the solder hardness is moderated and the stress on a ball is relaxed. Due to this, the stress does not concentrate on the solder joint which prolongs the lifetime. In this investigation, the thermal–electrical–mechanical coupling of electromigration on bumps containing a plastic solder is studied.

On electrochemical cell modeling as basis for predicting corrosion failures in plastic encapsulated microelectronics

Despite extensive research over the past decades, corrosion of aluminum bond pads is still a major reliability risk for plastic encapsulated microelectronics. Nowadays even an increase in susceptibility for corrosion is observed for new waferfab technologies and encapsulation materials during reliability tests. The recent trend for the new generation encapsulation materials is to decrease the glass transition temperature. As a result reliability tests could be performed at temperatures well above this temperature, such that traditionally used translations between test and operational lifetime, i.e. the acceleration factor, are no longer valid. Consequently, a new acceleration model for bond pad corrosion is required, which is capable of predicting the lifetime of products from test performed at temperatures above glass transition temperature. In this work we will show the merits of electrochemical cell modeling on the understanding of corrosion failures in microelectronics. The model is based on the Poisson-Nernst-Planck equation for the transport of ions coupled to a generalized Frumkin corrected Butler-Volmer equation for the kinetics of the electrochemical reactions. We present results as an example to clarify our approach.