Rafael Rosales

A very fast and quasi-accurate power-state-based system-level power modeling methodology

In this paper, we propose a novel system-level power modeling methodology that allows for very fast joint power-performance evaluation at specification phase. This methodology adopts approximately-timed task-accurate performance models and augments them with power-state-based power models to enable efficient simulation. A flexible method is also proposed to model complex dynamic power management policies so that their effects can be evaluated. We validate the accuracy of our methodology by comparing simulation results with measurements on a real mobile phone platform. Experimental results show that the simulated power profile matches very well with the measurements and it only takes about 100 ms to simulate a 20 ms GSM paging burst use case.

End-to-end power estimation for heterogeneous cellular LTE SoCs in early design phases

System-level power modeling and estimation is a non-trivial task for the architecture and power management strategies exploration during early design phases of a cellular LTE modem. It requires system architects to consider not only highly heterogeneous SoC architectures, but also various worldwide LTE network configurations and dynamic scheduling which impact modem power consumption significantly. In this work, we present an LTE end-to-end power model to enable a fast power consumption evaluation of different LTE modem system architecture options. The power model for digital elements is based on power states and refined by execution phases. For analogue/RF elements, the model is differentiated by each operational state consuming a constant power. The LTE power amplifier, as a major power contributor, is modeled at a detailed abstraction level using piece-wise polynomial equations with the consideration of band-to-band variations and the envelope tracking operation. Using this heterogeneous power modeling approach, different system design choices can be compared and explored holistically at a rather low modeling effort and a fast simulation speed. Moreover, the power estimation of the LTE modem takes into account the impact of real-life networks, which enables the easy adaptation to various network scenarios in early design phases. Thanks to this configurable end-to-end model, the productivity of a power modeling team can be improved by 10× to meet the challenge of increased exploration space in LTE modem concept design under tight time-to-market requirements.

MAESTRO— Holistic Actor-Oriented Modeling of Nonfunctional Properties and Firmware Behavior for MPSoCs

Modeling and evaluating nonfunctional properties such as performance, power, and reliability of embedded systems are tasks of utmost importance. In this article, we introduce MAESTRO, a methodology for the modeling and evaluation of nonfunctional properties and embedded firmware of MPSoC architecture components at the Electronic System Level (ESL). In contrast to existing design flows that provide predefined performance models, MAESTRO defines a flexible approach that allows to define virtual prototypes that can be easily customized and extended to evaluate multiple nonfunctional properties of interest at different levels of abstraction. In MAESTRO, a design is composed purely from actor-oriented models. This enables typical ESL features such as automatic design space exploration and synthesizability of HW and SW components, typically missing in very general design flows. Unique to MAESTRO is the separation and coordination of the interaction between application functionality, firmware, and performance models for the evaluation of nonfunctional properties, and their complex interactions within a single Model-of-Computation (MoC). The main advantages of MAESTRO are: (I) Extensible modeling of interdependent nonfunctional properties of heterogeneous MPSoC components; (II) high flexibility to investigate the appropriate trade-off between modeling effort and accuracy of nonfunctional property evaluators; (III) a holistic approach for modeling application functionality as well as firmware affecting the evaluation of nonfunctional properties. Regarding (II), we present a mobile baseband processor platform use-case, executing a GSM paging application. To demonstrate (I) and (III), we present the modeling of a complex ESL processor virtual prototype, running a soft real-time application and equipped with both a power and reliability manager.

On robust task-accurate performance estimation

Task-accurate performance estimation methods are widely applied in early design phases to explore different architecture options. These methods rely on accurate annotations generated by software profiling or real measurements to guarantee accurate results. However, in practice, such accurate annotations are not available in early design phases due to lack of source code and hardware platform. Instead, estimated mean or worstcase annotations are usually used, which makes the final result inaccurate because of the errors induced by the estimations, especially for designs with tight time constraints. In this paper, we propose a novel methodology that combines Distributionally Robust Monte Carlo Simulation with task-accurate performance estimation method to guarantee robust system performance estimation in early design phases, i.e., determining the lower bound of the confidence level of fulfilling a specific time constraint. Instead of using accurate annotations, our method only uses estimated annotations in the form of intervals and it does not make any assumptions of the distribution types of these intervals.

Multi-objective design space exploration for the optimization of the HEVC mode decision process

Finding the best possible encoding decisions for compressing a video sequence is a highly complex problem. In this work, we propose a multi-objective Design Space Exploration (DSE) method to automatically find HEVC encoder implementations that are optimized for several different criteria. The DSE shall optimize the coding mode evaluation order of the mode decision process and jointly explore early skip conditions to minimize the four objectives a) bitrate, b) distortion, c) encoding time, and d) decoding energy. In this context, we use a SystemC-based actor model of the HM test model encoder for the evaluation of each explored solution. The evaluation that is based on real measurements shows that our framework can automatically generate encoder solutions that save more than 60% of encoding time or 3% of decoding energy when accepting bitrate increases of around 3%.

Analysis and Exploitation of CTU-Level Parallelism in the HEVC Mode Decision Process Using Actor-Based Modeling

The new High-Efficiency Video Coding HEVC standard achieves much better compression ratios than previous ones by offering multiple coding modes, albeit with a significant increase over the required computational power especially at the encoder side. As the first major contribution, we propose a fine-grained parallelization of the encoding mode decision process using a SystemC actor-based model, exploiting multi-core platforms. Second, based on this model, we analyze achievable speedups compared to the single core sequential implementation of the HM-16.0 reference software. Using four different video sequences, we find that our approach achieves an equivalent rate-distortion performance for different quantization parameter values with a simulated encoding time improvement factor of upi¾źto

On confident task-accurate performance estimation

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Scenario-based energy estimation of heterogeneous integrated systems at system level

for a maximally parallelized mode decision process. Third, an HEVC encoder has a huge number of different standard-complying encoding modes to choose from for each encoded frame, making the exploration space almost impossible to be fully covered by a brute-force search. Here, we systematically investigate the trade-off in encoding time versus required number of processor cores by proposing a multi-objective Design Space Exploration DSE of the mapping of the parallelized mode decision tasks to processing resources, taking as optimization objectives the resulting bitrate, image quality, number of processor cores used, execution time, and total energy consumption.