Raghavan Subramaniyan

Techniques to improve motion compensation performance of H264 video decoder using a vector processor

Motion Compensation for video decoding in standards like H.264 requires significant amount of computation. This is primarily because of H.264 six-tap FIR filtering for sub-sample computation. These algorithms typically take more than 50% of the computational time on a RISC processor like ARM. Novel algorithms proposed through this paper can be employed for systems which use vector processors as video decode accelerators to accelerate this process. The proposed algorithms are implemented on H264 video decode system with ARM9 host-processor and RSVP vector processor as an accelerator for key decode algorithms. By employing the proposed algorithms we were able to accelerate the motion compensation module by more than 4 times as compared to plain RISC implementation. This is achieved by efficiently vectorizing data on which FIR-filtering and reconstruction algorithm is operated on, together with optimal representation of FIR-filtering and reconstruction algorithm itself on vector processor.