Rahima K. Mohammed

Experimental techniques for thermo-mechanical design in silicon validation platforms

Validation platforms are used to validate processors/chipsets to ensure Intel providing world-class quality and reliable products. In this paper, experimental methodologies of thermal, mechanical, acoustics, shock and vibration and ergonomic tests are demonstrated. These tests are essential to enable the boot-out-of-the-box model with increased complexities of the platforms while meeting the budget and schedule. Component level thermal testing data are correlated with CFD simulations to provide guidance for system simulations. The choice of second level thermal interface material (TIM2) was implemented using the detailed thermo-mechanical test data. Next, the acoustic tests are performed to meet acoustic safety requirements and to implement fan control to minimize system noise. Structural tests validated the retention designs based on Finite Element (FE) analyses. The packaged system level shock and vibration tests demonstrated the ability of the packaged system to avoid damages during shipping. Ergonomic chassis lifting tests illustrated in this paper assist to meet safety and ergonomic requirements for validation platforms. The experimental results guide the thermo-mechanical design decisions for validation platforms during the development and deployment phases. The work presented in this paper will serve as a guideline to support future thermo-mechanical designs of validation platforms.

High performance air-cooled temperature margining thermal tools for silicon validation

Thermal tools provide temperature margining capability by varying the case temperature at silicon thermal design power (TDP). They are used for process, voltage, temperature and frequency (PVTF) testing by Intels post-silicon validation customers across servers, desktops, mobile and graphics segments. Thermal margining tools are widely used in silicon debug validation by varying the case temperature over a wide operating range of specifications of the Silicon to i) validate the silicon, ii) accelerate fault detection, and iii) reduce escapes and identify bugs. Thermal tool is controlled by a thermal controller to provide a temperature set-point based on the device under tests (DUTs) case or junction diode temperature. Air cooled thermal tool (AC-TT) employs a controller card to achieve the margining capability by running the tools thermoelectric cooler (TEC), a Peltier device, within the optimal temperature range. AC-TT has an active heat sink design to remove the heat dissipated by the TEC and the silicon. Although AC-TT is expected to provide narrower range of margining capability due to the limitations of air cooling, they still can be an excellent solution for some specific thermal margining applications. Therefore, a new line of AC-TTs were developed for validation customers whose needs can be addressed without requiring costly controllers and noisy chillers while enhancing the user-experience. This paper presents the design improvement strategies implemented for developing the new line of CPU, Chipset and ASIC AC-TTs. Improved designs provide wider margining capability by using i) high performance active heat sink designs, ii) high power thermo-electric cooler (TEC), iii) cold plate designs compatible to keep out volume (KOV), iv) new choice of thermal interface material (TIM), and v) new retention design. This paper discusses the details of the design process and how multiple design strategies are implemented to finalize the design and to achieve the overall performance improvement while keeping the cost of the AC-TT low. The new line of AC-TT designs have performance improvement of 44% (∼25C) for 130W CPU TT compared to existing CPU AC-TT, of 32% (∼19C) for 60W chipset compared to existing chipset AC-TT, and of 41% (∼8C) compared to existing 15W PCH (Peripheral Component Hub) AC-TT. Design strategies provided here can be easily adapted to develop future generation of low-cost CPU, chipset, and ASIC AC-TTs with a wider margining capability.

Design challenges of thermal margining tools for silicon validation

Rapid advances in the semiconductor process technology have led to miniaturization of transistor features and advent of multi-core architecture. At the silicon-level while bus speeds, features and functionalities are increasing, at the system-level, there is a steady and incessant trend of volume reduction, compact component placement on the board and noise reduction. Thermal margining tools (TTs) based on a Peltier type thermo-electric-cooler (TEC) replace the cooling solution of the device under test (DUT). The thermal margining head is controlled by the thermal controller to provide a temperature set-point based on the DUTs case temperature. These TTs provide temperature margining capability of varying the case temperature from 5°C to 100°C at silicon thermal design power (TDP) are used for process, voltage, temperature, frequency (PVTF) testing, debug, acceleration of fault detection by Intels post-silicon validation customers across servers, desktops, mobile and graphics segments. This paper presents the thermo-mechanical design challenges of thermal margining tools. First, we present the details of the thermal margining head design for CPU, chipset and ASIC including the retention design for socketed/soldered down silicon as necessary. Second, we demonstrate how introduction of CFD modeling and retention design methodology has helped with the design optimization of the thermal head. This detailed methodology enabled designing and delivering thermal tools with predictability of the temperature margining range and improved quality of products delivered to validation customers while achieving significant cost saving of the tools. Third, we present the field issues, thermal performance degradation and failure modes of these thermal tools. Finally, we present the challenges ahead of us and the advancements we need from the rest of the industry specifically in TEC technology in designing small form factor thermal margining tools to address the shrinking KOV of the Silicon component placements on the board across the market segments to enable increasing bus speeds, features, functionalities and TDP/power density.

Acoustics management for server debug validation platforms

Combination of higher cooling power with the introduction of fully buffered dual in-line memory module (FBD) memory technology and accessibility requirements for server validation platform have driven cooling fan selection at relatively high speeds resulting in high acoustic noise. Most validation platforms are open systems and hence the acoustic noise becomes worse without system walls to act as sound barriers. This paper presents the implementation of the dynamic and hard-coding fan control schemes for validation platforms based on analyses from thermal simulations to reduce the noise. The studies showed that these acoustic management schemes can reduce the noise by 6-15dB depending on the fan choice.

Advanced Liquid Cooling Technology Evaluation for High Power CPUs and GPUs

Increasing thermal design power (TDP) trends with shrinking form factor requirements creates the need for advanced cooling technology development. This investigation proposes multiple innovative water cooler technologies to achieve higher thermal performance liquid-cooling (LC) solutions addressing the limitations of air-cooling (AC). High performance water cooler design options will also meet the miniaturization trends of computing market by providing scalable solution to address smaller board real-estate. This investigation serves multi-fold advantages: 1) introduces four water cooler technologies employing different fin base plate designs, diamond fins, micro-fins, skived micro-fins, and twisted diamond fins, along with an optimized flow distribution path design accompanying each cooler, 2) provides scalable thermal solutions, 3) addresses particle clogging via fin base plate as well as flow distribution path optimization, 4) addresses galvanic corrosion by eliminating the use of two dissimilar metals and introducing acrylic housing, 5) introduces acrylic housing for weight management. Results show that twisted diamond fin, micro-fin and skived micro-fin coolers provide up to 5°C performance improvement resulting in lower pressure drop across water cooler compared to diamond fin cooler and about 37°C improvement compared to air-cooled active heatsink solution.Copyright

Flow optimizer architecture designs in high powered computing coolant chambers

With the ever increasing trend of cramming more transistors on the silicon and the consequential increase in the thermal design power, combined with stacked die and multiple die configurations inside the package footprint, optimized coolant chambers becomes an imperative design need to remove heat efficiently from the silicon. Liquid cooling is investigated to efficiently meet the challenges of high heat loads on several different fin geometries, lowering thermal resistance, and lower noise. Branching flow evenly inside the coolant chamber is vital for optimal performance of the chamber. In this paper, we present computational investigations for improving the thermal performance of a liquid-cooled chamber by optimizing the coolant flow inside the chamber with the aid of novel symmetric baffles strategically located at the inlet and outlet. Flow animation visualization from CFD simulations also show that the baffle introduces turbulence inside the liquid-cooled chamber eliminating stagnant zones especially in the corners. A numerical conjugate convection in the channel and conduction on the fin plate/substrate heat transfer model was developed and setup to run for seven different fin geometries using Ansys Icepak CFD solver. A k-ε model was used to predict the turbulent flow and heat transfer through all the different finned coolant chamber. A new type of miniaturized fin, based on the NACA-0020 airfoil is introduced as a staggered array of pin fin configuration inside liquid cooled chambers and computationally investigated at several inlet velocities ranging from 0.5 m/s to 3.0 m/s (2000 ≤ Re ≤ 12,000) characterizing the variation of surface Nusselt number with Reynolds number. Surface Nusselt number, a dimensionless heat transfer coefficient is investigated along the surfaces of all the fins to predict the convective cooling capability of the fins being considered. Simulation results reveal that NACA-0020 airfoil fin structure with a 0.23 airfoil thickness-to chord length ratio, has the best performance compared against all the other fins investigated in this study. The findings from this investigation can improve thermal performance of liquid cooled heat sinks across a wide range of package powers.

Welcome to SEMI-THERM 32!

It is my honor and pleasure to welcome you to the SEMITHERM 32 conference, the 32nd annual conference on thermal design, management, measurement and characterization of Semiconductor components and systems. This premier international conference will be held at the DoubleTree by Hilton Hotel, San Jose, California, USA, on March 14–17, 2016. The SEMI-THERM conference is overseen by the SEMI-THERM Educational Foundation (STEF), an organization dedicated to providing worldwide educational opportunities and resources within the electronic thermal engineering community. SEMI-THERMs mission statement is “to provide an annual forum for the exchange of latest technical developments in thermal management of electronic devices, components and systems.” This is accomplished by offering a multifaceted program of events of interest to developers, practitioners and researchers from academia and industry in the field of electronics thermal management. This year the SEMI-THERM organizing and technical committee has invested tremendous efforts to put together a broad and exciting, high-quality technical program in tune with the mission of STEF covering the latest advances in its fields of expertise. Overall, I am confident that you will be able to gain new knowledge, grow your network and embrace new opportunities to advance your own career as well as enable your organizations to reach new heights of excellence, innovation and creativity.

TEC cracking in temperature margining liquid-cooled thermal tools in post-silicon validation

The thermal electric cooler (TEC) is a solid state heat pump and is a fundamental building block of liquid-cooled thermal tools used for temperature margining in platform validation systems. TECs are prone to cracking and thermal performance degradation during power cycling similar to those in flip-chip packages. A modeling methodology is developed to enable analysis of the thermal tool and understand better the stresses and deformations that the TEC go through during power cycling. TEC cracking and performance degradation have been perennial issues for liquid-cooled thermal tools. Prior method to deal with TEC reliability issues for thermal margining tools deployed in the field was to rework the thermal tools by refreshing the TECs. This is costly and time-consuming process and has a direct impact on the time to market of the silicon. In this paper, we introduce a combined computational fluid dynamics and finite element modeling techniques to explain the reliability issues observed in the TEC. This novel modeling methodology offers a physics-based analysis of the inner mechanics of the thermal margining tool. This paper focuses on a typical liquid-cooled thermal tool and uses experimental data to validate the model. The study also uses the model to do sensitivity analysis on Thermal Interface Material (TIM), fastening, and material properties. This technique can be used to reduce thermal stresses in the TEC, predict the performance of future thermal tool designs, optimize the performance of thermal tools, and extend their useful life while reducing the amount of reliability testing necessary during development. This is especially critical as the number and variety of thermal tools proliferate. This method can serve as a best known method (BKM) for future liquid-cooled thermal tool designs.

TIM selection criteria for silicon validation environment

Thermal interface materials (TIMs) are widely used as heat conductive medium between a heat source and a heat dissipating device. A high thermal performance TIM can provide a low thermal resistance path and thus improve the thermal management of the heat source. This paper presents various criteria for TIMs used in silicon validation environment in addition to the well-known criteria for high performance TIMs. Seven commercially available greases and eight different thermal pads were evaluated based on the requirements for use in the silicon validation environment. These criteria include thermal performance before and after subjected to elevated temperature, adhesiveness of the grease before and after subjected to elevated temperature, adhesiveness of the grease over multiple usages, compliance of the thermal pad, reusability of the thermal pad for multiple loading and unloading cycles, and severity of silicone bleed from the thermal pad under elevated temperature and pressure. In addition to these validation requirements of TIMs, there is an additional requirement of high cycle of reusability in the robotic testing environment to minimize human interface. Indium TIM, a metallic TIM, provides well over 500 reusability cycles. Adhesion issue with high Indium content becomes dominant at high temperature and needs to be well addressed to take advantage of the reusability characteristics of Indium TIM.

Thermo-mechanical design challenges in silicon validation platforms

Rapid advances in the semiconductor process technology have led to miniaturization of transistor features and advent of multi-core architecture. At the silicon-level while bus speeds, features and functionalities are increasing, at the system-level, there is a steady and incessant trend of volume reduction, compact component placement on the board and noise reduction. These silicon and system trends make the thermo-mechanical designs challenging. Validation platforms are used to validate microprocessors/chipsets to ensure world-class quality and reliable Intel products. These platforms usually have an open chassis to allow ease of accessibility for silicon debug. In this paper, we present the design challenges and opportunities faced in validation from thermo-mechanical perspective. The requirements for sockets, nominal cooling thermal solutions, temperature margining thermal tools, and limited Keep-Out-Volume (KOV) on the motherboard create significant challenges in designing mechanical retention mechanism for sockets, thermal and thermal tools. We present the design methodology of active air cooling coupled with mechanical retention. We also demonstrate the design challenges and innovations of peltier-based temperature margining thermal tools used for fault detection acceleration. These methodologies can serve as Best Known Methods (BKMs) for delivering novel designs for nominal cooling and temperature margining thermal tools to address the small factor, dense pad-pitch, high pin-count and high TDP challenges of validation platforms.