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Dive into the research topics where Raimund Kirner is active.

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Featured researches published by Raimund Kirner.


design, automation, and test in europe | 2005

Automatic Timing Model Generation by CFG Partitioning and Model Checking

Ingomar Wenzel; Bernhard Rieder; Raimund Kirner; Peter P. Puschner

We present a new measurement-based worst-case execution time (WCET) analysis method. Exhaustive end-to-end measurements are computationally intractable in most cases. Therefore, we propose to measure execution times of subparts of the application. We use heuristic methods and model checking to generate test data, forcing the execution of selected paths to perform run-time measurements. The measured times are used to calculate the WCET in a final computation step. As we operate on the source code level, our approach is platform independent except for the run-time measurements performed on the target host. We show the feasibility of the required steps and explain our approach by means of a case study.


leveraging applications of formal methods | 2008

Measurement-Based Timing Analysis

Ingomar Wenzel; Raimund Kirner; Bernhard Rieder; Peter P. Puschner

In this paper we present a measurement-based worst-case execution time (WCET) analysis method. Exhaustive end-to-end execution-time measurements are computationally intractable in most cases. Therefore, we propose to measure execution times of subparts of the application code and then compose these times into a safe WCET bound.


international conference on quality software | 2005

Principles of timing anomalies in superscalar processors

Ingomar Wenzel; Raimund Kirner; Peter P. Puschner; Bernhard Rieder

The counter-intuitive timing behavior of certain features in superscalar processors that cause severe problems for existing worst-case execution time analysis (WCET) methods is called timing anomalies. In this paper, we identify structural sources potentially causing timing anomalies in superscalar pipelines. We provide examples for cases where timing anomalies can arise in much simpler hardware architectures than commonly supposed (i.e., even in hardware containing only in-orderfunctional units). We elaborate the general principle behind timing anomalies and propose a general criterion (resource allocation criterion) that provides a necessary (but not sufficient) condition for the occurrence of timing anomalies in a processor. This principle allows to state the absence of timing anomalies for a specific combination of hardware and software and thus forms a solid theoretic foundation for the time-predictable execution of real-time software on complex processor hardware.


euromicro conference on real time systems | 2002

Fully automatic worst-case execution time analysis for MATLAB/Simulink models

Raimund Kirner; Roland Lang; Gerald Freiberger; Peter P. Puschner

In todays technical world (e.g., in the automotive industry), more and more purely mechanical components get replaced by electro-mechanical ones. Thus the size and complexity of embedded systems steadily increases. To cope with this development, comfortable software engineering tools are being developed that allow a more functionality-oriented development of applications. The paper demonstrates how worst-case execution time (WCET) analysis is integrated into such a high-level application design and simulation tool MATLAB/Simulink-thus providing a higher-level interface to WCET analysis. The MATLAB/Simulink extensions compute and display worst-case timing data for all blocks of a MATLAB/Simulink simulation, which gives the developer of an application valuable feedback about the correct timing of the application being developed. The solution facilitates a fully-automated WCET analysis, i.e., in contrast to existing approaches the programmer does not have to provide path information.


international symposium on object component service oriented real time distributed computing | 2008

Obstacles in Worst-Case Execution Time Analysis

Raimund Kirner; Peter P. Puschner

The analysis of the worst-case execution time (WCET) requires detailed knowledge of the program behavior. In practice it is still not possible to obtain all needed information automatically. In this paper we present the current state of the art of WCET analysis and point to the main problems to be solved. The most eminent problem is the state problem, i.e., the precise determination of possible processor states at different program locations. The path problem refers to the fact that current tools are not able to calculate all (in)feasible paths automatically. We discuss how the main open problems manifest themselves in static and in measurement-based WCET analysis methods.


euromicro conference on real-time systems | 2001

Transformation of path information for WCET analysis during compilation

Raimund Kirner; Peter P. Puschner

Performing worst-case execution time (WCET) analysis on machine code with program path annotation provided at high-level source code level requires the transformation of path annotations from the source-code level to assembly/object-code level. This path-information transformation can be done outside or integrated into the compiler during code compilation. The first approach is easier to implement but lacks for the support of strong code optimizations performed by the compiler because the external tool would have to make guesses about optimizations. In this paper we present an approach for the program code compilation that integrates the transformation of program path information into the compiler. Path information is transformed through all compiler stages to the adequate path information for the corresponding assembly code level. The WCET analysis tool processes the program at assembly code level with the correctly transformed program-path information to obtain accurate runtime bounds. Several experiments were performed to demonstrate the importance of supporting the transformation of path-information in aggressively optimizing compilers.


software technologies for embedded and ubiquitous systems | 2005

Measurement-based worst-case execution time analysis

Ingomar Wenzel; Raimund Kirner; Bernhard Rieder; Peter P. Puschner

In the last years the number of electronic control systems has increased significantly. In order to stay competitive more and more functionality is integrated into more and more powerful and complex computer hardware. Due to these advances in control systems engineering new challenges for analyzing the timing behavior of real-time computer systems arise. The two identified main challenges are execution-time modeling of the hardware and the path problem that forbids capturing the worst-case execution time (WCET) by end-to-end measurements due to limits in computational complexity. This work presents the cornerstones of our new measurement-based WCET analysis method that successfully addresses these problems. We clearly identify our research goals and the relevance of our research. Especially, the novel aspects of our approach are emphasized. The conclusion is formed by a brief presentation of an industrial-size case study application.


international symposium on object component service oriented real time distributed computing | 2005

Classification of WCET analysis techniques

Raimund Kirner; Peter P. Puschner

Worst-case execution time (WCET) analysis has become an active research area over the last decade. Various techniques have been developed to improve the WCET calculation methods for numerous features of the hardware. In parallel, attention has been paid to integrate the analysis techniques into modern software engineering processes. In this paper we give an overview about the different aspects of WCET analysis. We clarify terms and categorise features of WCET analysis tools. Therefore we present a generic framework for WCET analysis and describe its fundamental operations. We present a classification scheme to test the applicability of WCET analysis tools for certain analysis requirements.


international conference on computer safety, reliability, and security | 2012

Compiling for time predictability

Peter P. Puschner; Raimund Kirner; Benedikt Huber; Daniel Prokesch

Within the T-CREST project we work on hardware/software architectures and code-generation strategies for time-predictable embedded and cyber-physical systems. In this paper we present the single-path code generation approach that we plan to explore and implement in a compiler prototype for a time- predictable processor. Single-path code generation produces code that forces every execution to follow the same trace of instructions, thus supporting time predictability and simplifying the worst-case execution-time analysis of code. The idea of the single-path generation and details about the code-generation rules of the compiler can be found in this work.


Real-time Systems | 2010

Transforming flow information during code optimization for timing analysis

Raimund Kirner; Peter P. Puschner; Adrian Prantl

The steadily growing embedded-systems market comprises many application domains in which real-time constraints must be satisfied. To guarantee that these constraints are met, the analysis of the worst-case execution time (WCET) of software components is mandatory. In general WCET analysis needs additional control-flow information, which may be provided manually by the user or calculated automatically by program analysis. For flexibility and simplicity reasons it is desirable to specify the flow information at the same level at which the program is developed, i.e., at the source level. In contrast, to obtain precise WCET bounds the WCET analysis has to be performed at machine-code level. Mapping and transforming the flow information from the source-level down to the machine code, where flow information is used in the WCET analysis, is challenging, even more so if the compiler generates highly optimized code.In this article we present a method for transforming flow information from source code to machine code. To obtain a mapping that is safe and accurate, flow information is transformed in parallel to code transformations performed by an optimizing compiler. This mapping is not only useful for transforming manual code annotations but also if platform-independent flow information is automatically calculated at the source level.We show that our method can be applied to every type of semantics-preserving code transformation. The precision of this flow-information transformation allows its users to calculate tight WCET bounds.

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Peter P. Puschner

Vienna University of Technology

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Michael Zolda

Vienna University of Technology

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Adrian Prantl

Lawrence Livermore National Laboratory

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Albrecht Kadlec

Vienna University of Technology

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Frank Penczek

University of Hertfordshire

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Ingomar Wenzel

Vienna University of Technology

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Bernhard Rieder

Vienna University of Technology

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Jens Knoop

Vienna University of Technology

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Sven Bünte

Vienna University of Technology

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