Rainer Fink

A DSP-based mixed-signal waveform generator

As it currently stands, waveform generators are being employed in many diverse areas, such as radar applications, communication systems, simulation, and testing. There is considerable interest in exploring the beacon of opportunity posed by using digital signal processor (DSP)-based systems to replace costly and inadequate conventional waveform generators. The availability of high performance DSPs allows for the design of highly flexible equipment capable of real-time processing. The arbitrary waveform generator introduced in this paper consists of a DSP, a FIFO memory, a video palette, and a PC interface. A program running on the PC creates a digital representation of a waveform according to user parameters and sends it to the DSPs RAM. The DSP algorithmically converts the digital representation to a point-by-point representation of the desired analog signal. The data points are sent to the FIFO buffer, which latches the data to a video palette that serves a three-channel digital-to-analog converter. The system employs a high-speed serial port interface to communicate with a PC, to allow for readily programmed signals. In addition to the production of traditional signals, such as sinusoids and squarewaves, a mathematical tool known as splines is employed to aid in the development of customized arbitrary waveforms. Finally, a picture of our new device is presented in the paper.

A spline function, DSP based mixed-signal arbitrary waveform generator

As it currently stands, waveform generators are being employed in many diverse areas such as communication systems, radar applications, simulation, and testing. The arbitrary waveform generator introduced in this paper consists of a DSP (Digital Signal Processor), a FIFO memory, a video palette, and a PC interface. A program running on the PC creates a digital representation of a waveform according to user parameters and sends it to the DSPs RAM. The DSP algorithmically converts the digital representation to a point-by-point representation of the desired analog signal. The data points are sent to the FIFO buffer, which latches the data to the video palette that serves as the digital to analog converter. The system uses JTAG and a high-speed serial port interface to communicate with the PC, to allow for readily programmed signals. In addition to the production of traditional signals such as sinusoids and squarewaves, a mathematical tool known as splines will be employed to aid in the development of customized arbitrary waveforms. A picture of our new device is presented in the paper, in addition to laboratory measurements.

A DSP-based technique for high-speed A/D conversion to generate coherently sampled sequences

This paper presents a digital signal processor (DSP) based device that will digitize a high speed analog signal. The device takes advantage of a new undersampling strategy which employs two clocks, rather than employing a traditional swept delay generator. The random access memory of the DSP and the signal processing capabilities are employed so that the signal is sampled over an integer number of cycles, thus insuring coherency in the sampled data set. Coherency is important property that eliminates additional unwanted discontinuities in a data set which introduces unwanted artifacts in the signals spectral content. An illustration of the new device is presented in the paper, in addition to laboratory measurements. The results also indicate that the new technique is competitive with solutions that exist in the current literature.

Assessment and improvement of intelligent controllers for elevator energy efficiency

In recent years, several measures are being taken to conserve power with a goal towards energy savings without degradation in performance. In this paper we develop an algorithm to achieve notable energy savings in elevator systems. Operation of an elevator can be classified into two modes-running mode and stand-by mode. We design an energy-saving elevator system capable of manipulating its speed in running mode. Speed is varied based on the load carried and acceleration based on the number of floors to travel. The total travel time of the system is to be considered for enhancing its overall performance. The algorithm is tested on varied traffic patterns: 1) Non-peak hours and 2) Peak hours. The final results are compared with constant speed elevators and tabulated. This method produces a 12.35% energy savings and 5.49% reduction in travel time during non-peak hours and 5.06% energy savings and 1.32% reduction in travel time during peak hours of traffic intensity.

Design of a CORDIC processor for mixed-signal A/D conversion

This paper proposes a new method which offers a high level of synchronization between a source, which is primarily digital, that generates a test signal and the analog-to-digital converter (ADC) that will sample it. By using a single clock to control the source, a clock divider may be used to derive a clock that will trigger an ADC at the appropriate times to produce a coherently sampled data set. Thus, the timing of the waveform and the ADC will be accurately synchronized; moreover, since test time is a valuable commodity, a predictable number of clock cycles can be issued in order to generate a sampled data set. A computer simulation is given which fully characterizes the theoretical aspects of this paper. In addition, selected laboratory measurements are also given for discussion.

Assessment and improvement of elevator controllers for energy efficiency

In recent years, several measures are being taken to conserve power with a goal towards energy savings without degradation in performance. In this paper we develop an algorithm to achieve notable energy savings in elevator systems. Operation of an elevator can be classified into two modes-running mode and stand-by mode. We design an energy-saving elevator system capable of manipulating its speed in running mode. Speed is varied based on the load carried and acceleration based on the number of floors to travel. Also choosing an appropriate range of speed is investigated. The total travel time of the system is to be considered for enhancing its overall performance. The algorithm is tested on varied traffic patterns: 1) Non-peak hours and 2) Peak hours. The final results are compared with constant speed elevators and tabulated. This method produces a 12.35% energy savings and 5.49% reduction in travel time during non-peak hours and 5.06% energy savings and 1.32% reduction in travel time during peak hours of traffic intensity.

An In Situ Study of the Habits of Users That Affect Office Chair Design and Testing

Objective: The purpose of this study was to perform an in situ assessment of office seating habits that influence chair testing and design. Background: Many chair testing parameters were derived decades ago when the average weight of people within the United States was dramatically lower and the office work tasks less computer based. Method: For the study, 51 participants were randomly selected from Brazos Valley, Texas, businesses to participate in 8-hr assessments of office seating habits. Overall results were compared with current chair testing and design assumptions. Data were collected through written survey and through data logging of seat and back contact pressure and duration with the use of the X-SENSOR™ pressure mapping device and software. Additionally, 1 day per participant of caster roll distance was recorded with the use of a caster mounted digital encoder. Participants were grouped by body mass index (BMI) and weight (BMI <35 and weight <102 kg or BMI >35 and weight >102 kg). Results: It was determined that a significant difference did exist between the groups in mean seat time per shift (p < .001), back cycles per shift (p < .002), seat cycles per shift (p < .01), and caster distance rolled per shift (p < .001). Conclusion: Several key parameters and assumptions of current chair test methods and design specifications may no longer be valid for the upper quartile of weight range of the current U.S. population. Application: The data collected in this study will enable engineers to determine whether revision of design standards for testing office seating for both normal weight and extremely obese workers is indicated.

Performance evaluation of energy efficient intelligent elevator controllers

Recently, several measures are being taken to conserve energy without degradation in performance. To achieve notable energy savings in elevator systems, in this paper we develop and experimentally test an algorithm. Operation of an elevator can be classified into two modes: running mode and stand-by mode. We design an elevator system capable of energy-saving by manipulating its speed in running mode. Speed is varied based on the difference of load carried and the counter weight. A miniature elevator model is used to carry out the experiments and to collect energy data. The algorithm is tested on different traffic patterns: 1) pre-determined pattern, and 2) random pattern. Voltage and current samples are collected from the miniature elevator model, The final energy data of variable speed system are calculated and compared with energy data of constant speed system. This proposed method results in a 3.715% energy savings for pre-determined traffic pattern and 8.7612% energy savings for random traffic patterns.

Waveform synthesis via splines

As it currently stands, waveform generators are being employed in many diverse areas such as communication systems, radar applications, simulation, and testing. Thus, the objective here is to develop an algorithm for a waveform generator capable of synthesizing analog signals from a specified collection of discrete signal points, and polynomial splines are employed to develop a smooth curve (continuous derivatives) connecting these points. Texas Instruments recently released its 720 MHz digital signal processor (worlds fastest), and the purpose of this brief paper is to add to the body of knowledge associated with splines and digital to analog conversion.