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Publication
Featured researches published by Rajasekhar Venigalla.
international electron devices meeting | 2014
Qing Liu; B. DeSalvo; Pierre Morin; Nicolas Loubet; S. Pilorget; F. Chafik; S. Maitrejean; E. Augendre; D. Chanemougame; S. Guillaumet; H. Kothari; F. Allibert; B. Lherron; B. Liu; Y. Escarabajal; Kangguo Cheng; J. Kuss; Miaomiao Wang; R. Jung; S. Teehan; T. Levin; Muthumanickam Sankarapandian; Richard Johnson; J. Kanyandekwe; Hong He; Rajasekhar Venigalla; Tenko Yamashita; Balasubramanian S. Haran; L. Grenouillet; M. Vinet
We report FDSOI devices with a 20nm gate length (L<sub>G</sub>) and 5nm spacer, featuring a 20% tensile strained Silicon-on-Insulator (sSOI) channel NFET and 35% [Ge] partially compressive strained SiGe-on-Insulator (SGOI) channel PFET. This work represents the first demonstration of strain reversal of sSOI by SiGe in short channel devices. At V<sub>dd</sub> of 0.75V, competitive effective current (I<sub>eff</sub>) reaches 550/340 μA/μm for NFET, at I<sub>off</sub> of 100/1 nA/μm, respectively. With a fully strained 30% SGOI channel on thin BOX (20nm) substrate and V<sub>dd</sub> of 0.75V, PFET I<sub>eff</sub> reaches 495/260 μA/μm, at I<sub>off</sub> of 100/1 nA/μm, respectively. Competitive sub-threshold slope and DIBL are reported. With the demonstrated advanced strain techniques and short channel performance, FDSOI devices can be extended for both high performance and low power applications to the 10nm node.
international electron devices meeting | 2016
Gen Tsutsui; Ruqiang Bao; Kwan-yong Lim; Robert R. Robison; Reinaldo A. Vega; Jie Yang; Zuoguang Liu; Miaomiao Wang; Oleg Gluschenkov; Chun Wing Yeung; Koji Watanabe; Steven Bentley; Hiroaki Niimi; Derrick Liu; Huimei Zhou; Shariq Siddiqui; Hoon Kim; Rohit Galatage; Rajasekhar Venigalla; Mark Raymond; Praneet Adusumilli; Shogo Mochizuki; Thamarai S. Devarajan; Bruce Miao; B. Liu; Andrew M. Greene; Jeffrey Shearer; Pietro Montanini; Jay W. Strane; Christopher Prindle
Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.
advanced semiconductor manufacturing conference | 2008
Chienfan Yu; Javier Ayala; Cung D. Tran; Anthony Santiago; Eric Meyette; Elizabeth Hampton; Garrett W. Oakley; Kenneth A. Bandy; Timothy M. McCormack; Rajasekhar Venigalla; Frederick A. Scholl
During manufacturing transitioning from 90 nm to 65 nm node in IBMs 300 mm fab, FEOL (front end of line) defect pareto shifted as a result of the changes in integration scheme. By combining the optically based in-line inspection and electrical kerf test, key yield detractors were identified and addressed. Not all optically detected defects are true killers. Wafer functional test and physical failure analysis provided the ultimate determination for the significance of detractors.
Archive | 2012
Emre Alptekin; Dong-Ick Lee; Viraj Y. Sardesai; Cung D. Tran; Jian Yu; Reinaldo A. Vega; Rajasekhar Venigalla
Archive | 2004
Rajasekhar Venigalla; James W. Hannah; Timothy M. McCormack; Robert M. Merkling
Archive | 2011
Emre Alptekin; Dong-Ick Lee; Viraj Y. Sardesai; Cung D. Tran; Jian Yu; Reinaldo A. Vega; Rajasekhar Venigalla
Archive | 2015
Su Chen Fan; Balasubramanian Pranatharthiharan; Rajasekhar Venigalla
Archive | 2011
Rajasekhar Venigalla; Michael V. Aquilino; Massud Aminpur; Michael P. Belyansky; Unoh Kwon; Christopher D. Sheraw; Daewon Yang
Archive | 2007
Yaocheng Liu; Zhijiong Luo; Katherine L. Saenger; Chun-Yung Sung; Rajasekhar Venigalla; Haizhou Yin
Archive | 2017
Hari V. Mallela; Reinaldo A. Vega; Rajasekhar Venigalla