Rajeev Muralidhar

Investigating the potential of application-centric aggressive power management for HPC workloads

Energy efficiency of large-scale data centers is becoming a major concern not only for reasons of energy conservation, failures, and cost reduction, but also because such sys tems are soon reaching the limits of power available to them. Like High Performance Computing (HPC) systems, large-scale clu ster-based data centers can consume power in megawatts, and of all the power consumed by such a system, only a fraction is used for actual computations. In this paper, we study the potential of application-centric aggressive power management of data centers resources for HPC workloads. Specifically, we consider power management mechanisms and controls (currently or soon to be) available at different levels and for different subsystems, and leverage several innovative approaches that have been taken to tackle this problem in the last few years, can be effectively used in a application-aware manner for HPC workloads. To do this, we first profile sta ndard HPC benchmarks with respect to behaviors, resource usage and power impact on individual computing nodes. Based on a power and latency model and the workload profiles, we develop an algorithm that can improve energy efficiency with little or no performance loss. We then evaluate our proposed algorithm through simulations using empirical power characterization and quantification. Finally, we validate the simulation results with actual executions on real hardware. The obtained results show that by using application aware power management, we can re-du ce the average energy consumption without significant penalty in performance. This motivates us to investigate autonomic approaches for application-aware aggressive power management and cross layer and cross function predictive subsystem level power management for large-scale data centers.

A distributed object infrastructure for interaction and steering

This paper presents the design, implementation and experimental evaluation of DIOS (Distributed Interactive Object Substrate), an interactive object infrastructure to enable the runtime monitoring, interaction and computational steering of parallel and distributed applications. DIOS enables application objects (data structures, algorithms) to be enhanced with sensors and actuators so that they can be interrogated and controlled. Application objects may be distributed (spanning many processors) and dynamic (be created, deleted, changed or migrated). Furthermore, DIOS provides a control network that interconnects the interactive objects in a parallel/distributed application and enables external discovery, interrogation, monitoring and manipulation of these objects at runtime. DIOS is currently being used to enable interactive visualization, monitoring and steering of a wide range of scientific applications, including oil reservoir, compressible turbulence and numerical relativity simulations. Copyright

Enabling interactive and collaborative oil reservoir simulations on the Grid

Grid‐enabled infrastructures and problem‐solving environments can significantly increase the scale, cost‐effectiveness and utility of scientific simulations, enabling highly accurate simulations that provide in‐depth insight into complex phenomena. This paper presents a prototype of such an environment, i.e. an interactive and collaborative problem‐solving environment for the formulation, development, deployment and management of oil reservoir and environmental flow simulations in computational Grid environments. The project builds on three independent research efforts: (1) the IPARS oil reservoir and environmental flow simulation framework; (2) the NetSolve Grid engine; and (3) the Discover Grid‐based computational collaboratory. Its primary objective is to demonstrate the advantages of an integrated simulation infrastructure towards effectively supporting scientific investigation on the Grid, and to investigate the components and capabilities of such an infrastructure. Copyright

A Distributed Object Infrastructure for Interaction and Steering

This paper presents the design, implementation and experimental evaluation of DIOS, an infrastructure for enabling the runtime monitoring and computational steering of parallel and distributed applications. DIOS enables existing application objects (data structures) to be enhanced with sensors and actuators so that they can be interrogated and controlled at runtime. Application objects can be distributed (spanning many processors) and dynamic (be created, deleted, changed or migrated). Furthermore, DIOS provides a control network that manages the distributed sensors and actuators and enables external discovery, interrogation, monitoring and manipulation of these objects at runtime. DIOS is currently being used to enable interactive monitoring and steering of a wide range of scientific applications, including oil reservoir, compressible turbulence and numerical relativity simulations.

Exploring cross-layer power management for PGAS applications on the SCC platform

High-performance parallel computing architectures are increasingly based on multi-core processors. While current commercially available processors are at 8 and 16 cores, technological and power constraints are limiting the performance growth of the cores and are resulting in architectures with much higher core counts, such as the experimental many-core Intel Single-chip Cloud Computer (SCC) platform. These trends are presenting new sets of challenges to HPC applications including programming complexity and the need for extreme energy efficiency. In this paper, we first investigate the power behavior of scientific Partitioned Global Address Space (PGAS) application kernels on the SCC platform, and explore opportunities and challenges for power management within the PGAS framework. Results obtained via empirical evaluation of Unified Parallel C (UPC) applications on the SCC platform under different constraints, show that, for specific operations, the potential for energy savings in PGAS is large; and power/performance trade-offs can be effectively managed using a cross-layer approach. We investigate cross-layer power management using PGAS language extensions and runtime mechanisms that manipulate power/performance tradeoffs. Specifically, we present the design, implementation and evaluation of such a middleware for application-aware cross-layer power management of UPC applications on the SCC platform. Finally, based on our observations, we provide a set of insights that can be used to support similar power management for PGAS applications on other many-core platforms.

An Architecture for Web-Based Interaction and Steering of Adaptive Parallel/Distributed Applications

This paper presents an architecture for web-based interaction and steering of parallel/distributed scientific applications. The architecture is composed of detachable thin-clients at the front-end, a network of web servers in the middle, and a control network of sensors, actuators and interaction agents at the back-end. The interaction servers enable clients to connect to, and collaboratively interact with registered applications using a conventional browser. The application control network enables sensors and actuators to be encapsulated within, and directly deployed with the computational objects. Interaction agents resident at each computational node register the interaction objects and export their interaction interfaces. An application interaction gateway manages the overall interaction through the control network of interaction agents and objects. It uses Java proxy objects that mirror computational objects to enable them to be directly accessed by the interaction web-server. The presented architecture is part of an ongoing effort to develop and deploy a web-based computational collaboratory that enables geographically distributed scientists and engineers to collaboratively monitor and control distributed applications.

Experiences with a Private Enterprise Cloud: Providing Fault Tolerance and High Availability for Interactive EDA Applications

Silicon Design and Electronic Design Automation (EDA) business is highly competitive and time to market is of utmost importance in the semiconductor industry where companies put in a lot of effort to make sure that the first silicon is as healthy as possible. Hence it is imperative that the EDA compute environment provides maximum uptime to design engineers by utilizing several different High Performance Computing (HPC) technologies. In this paper we present Intels EDA compute infrastructure, along with a detailed software and system architecture for supporting workload checkpointing, restoration and migration for specifically EDA jobs that are interactive in nature. We also describe our experiences in providing high availability for such EDA applications using existing popular HA/FT techniques. We believe that this is one of the few detailed descriptions of the EDA compute infrastructure of a large and complex semiconductor design company and that this will be useful in addressing future HPC challenges for EDA workloads as HPC technologies mature and evolve.

Performance of Real-Time Traffic in EDCA-BASED IEEE 802.11 b/g WLANS

The IEEE 802.11e draft specification is intended to solve the performance problems of WLANs for real time traffic by extending the original 802.11 medium access control (MAC) protocol and introducing priority access mechanisms in the form of the enhanced distributed channel access mechanism (EDCA) and hybrid coordination channel access (HCCA). The draft standard comes with a lot of configurable parameters for channel access, admission control, etc. but it is not very clear how real time traffic actually performs with respect to capacity and throughput in such WLANs that deploy this upcoming standard. In this report we have provided detailed simulation results on the performance of enterprise-anticipated real time VoIP application and collaborative video conferencing in presence of background traffic in EDCA-based IEEE 802.11 WLANs. We estimate the channel capacity and acceptable load conditions for some important enterprise usage scenarios. Subsequently, admission control limits are experimentally derived for these usage scenarios for voice and video traffic. Our simulations show that admission control greatly helps in maintaining the quality of admitted voice calls and video conferencing sessions that are prioritized as per EDCA mechanisms within acceptable channel load conditions. The use of admission control allows admitted voice calls and video sessions to retain their throughput and delay characteristics while unadmitted traffic (voice/video streams) greatly suffer from poor quality (delays, packet drops, etc.) as the channel load increases

On a rewriting strategy for dynamically managing power constraints and power dissipation in SoCs

We present a novel and highly automated technique for dynamic system level power management of System-on-a-Chip (SoC) designs. We present a formal system to represent power constraints and power intent as rules. We also present a Term Rewriting Systems based rule rewriting engine as our dynamic power manager. We provide a notion of formal correctness of our rule engine execution and provide a robust algorithm to dynamically and automatically manage power consumption in large SoC designs. There are two fundamental building blocks at the core of our technique. First, we present a powerful formal system to capture power constraints and power intent as rules. This is a self-checking system and will automatically flag conflicting constraints or rules. Next, we present a rewriting strategy for managing power constraint rules using a formal deductive logic technique specially honed for dynamic power management of SoC designs. Together, this provides a common platform and representation to seamlessly cooperate between hardware and software constraints to achieve maximum platform power optimization dynamically during execution. We demonstrate our technique in multiple contexts on an SoC design of the state-of-the-art next generation Intel smartphone platform.

TaskFolder: Dynamic and Fine-Grained Workload Consolidation for Mobile Devices

Despite the resource-constrained environment associated with mobile devices, the Android task scheduler tries to spread the workload equally among all CPU cores. While this is a sensible use of resources in desktop or server environments, it is inefficient for mobile devices, because they usually have lower computing demand and require single-user-perceptible performance guaran-tees. As a result, spreading tasks to all cores does not improve per-formance, increases energy consumption, and can cause perfor-mance issues when multiple mobile virtual machines attempt to engage as many cores as possible. To address this problem, we propose TaskFolder, a multi-core management scheme implemented on top of the task scheduler. TaskFolder attempts to compute the minimum number of cores required to perform the current workload without sacrificing per-formance, and schedules tasks to only that minimal number of cores. This number is called the Core Concurrency and is calculated based on past task dynamics. Experimental results of a case study show that TaskFolder saves an average of 19% and up to 48% of CPU power over a set of mobile applications on the latest Intel mobile platform.