Rajesh Mehra

Electrical and optical properties of Ge20SbxSe80−x thin films

Abstract The mechanism of incorporation of metallic antimony in amorphous films of the Ge 20 Sb x Se 80−x (5⩽ X ⩽25) system is studied by measuring the d.c. conductivity and optical absorption. It is observed that the addition of antimony increases the d.c. conductivity and decreases the optical gap of the system. The d.c. conductivity variation over the measured compositional range is analysed using the chemically ordered network model, which forms the microscopic molecular species of the system. An exponential dependence of the pre-exponential factor on activation energy is interpreted on the basis of the Meyer-Neldel rule. The change in the optical gap associated with antimony doping is explained in terms of defect states.

A.c. conduction in the amorphous Ge—Sb—Se system

Abstract A.c. and d.c. conductivities of amorphous films of Ge—Sb–Se have been investigated for different Sb: Se ratios, keeping the Ge content constant at 20 at. %. The a.c. conductivity [sgrave](ω, T) in the frequency range 0•5-10•0 kHz is found to obey the law [sgrave](ω, T) = Aω3. The exponent s is found to decrease with increasing temperature and Sb content, which is inconsistent with the quantum-mechanical tunnelling model. A strong temperature dependence of the a.c. conductivity [sgrave](ω, T) and exponent s in the entire range of temperatures and frequencies is reasonably interpreted by the correlated barrier hopping model, taking into account the contribution of both single polarons and bipolarons. The values of the energy of bound states, the correlation energy and the Fermi energy are estimated from the best fit between theoretical and experimental results. It is observed that the correlation energy increases while the energy of bound states decreases with increasing Sb content. The decrease in...

Influence of anodisation time, current density and electrolyte concentration on the photoconductivity spectra of porous silicon

Abstract Porous silicon layers emitting red photoluminescence (PL) have been prepared by the anodisation of p-type 〈100〉 monocrystalline Si substrate in different HF concentrations. The steady state photoconductivity of porous silicon (PS) layers as a function of electrolyte concentration, anodisation time and current density has been studied. The photoconductivity (PC) peak was observed to shift towards the shorter wavelength with the decrease in the crystallite size and it was interpreted to be the result of band gap widening. The recombination is found to have contribution from both the monomolecular and the bimolecular processes.

Optimized design and performance analysis of Johnson counter using 45 nm technology

Sequential circuits largely contribute to the power dissipation and propagation delay in a digital system. Low power, less delay and area efficient sequential circuit design has been the major concern for VLSI designers. The selection of optimized design technology plays a key role in achieving the above parameters. A counter is a sequential circuit having wide application area in microcontroller circuits including PLL, Digital to Analog converters, signal generators, signal synthesizers etc. In this paper a low power, high speed and cost efficient 4 bit Johnson counter is proposed. Deployed flip flop circuit uses 14 transistors to realize the negative edge triggered master slave D flip flop operation. Performance and cost of the proposed counter is compared against the conventional counter. The proposed design is found 48.86 % faster with having 43.22 % lesser power dissipation than conventional design. The transistor requirements in the proposed counter is also 69.5 % lesser making it an optimized design in terms of area.

Power and speed efficient ripple counter design using 45 nm technology

A very high speed, power and area efficient asynchronous and synchronous up/down counter is required in many applications viz. digital memories, ADCs, DACs, microcontroller circuits, frequency dividers, frequency synthesizer etc. Lower area, high speed and low power consumption may met by reducing size of hardware. Hence as the applications are increasing, demand for smaller size and longer life batteries increases This paper derives area, power and speed efficient structure for 3-bit asynchronous up counter for VLSI designing as the size of chip is reducing day by day. As demonstrated in this paper that by using proposed flip flop for the designing of 3-bit asynchronous up counter, number of transistor count is reduced by 69.56%, power is reduced by 46.05% and speed is increased by 49.8% compare to conventional design.

Vision based computer mouse control using hand gestures

This paper delineates a vision based interface for regulating a computer mouse via 2D hand gestures. The evolution of Human Computer Interaction (HCI) has diverted the interest of researchers towards natural interaction techniques in recent years. Numerous applications of real time hand gesture based recognition in the real world have been deployed where we interact with computers. Hand gestures rely upon camera based color detection technique. This method mainly focuses on the use of a Web Camera to develop a virtual HCI device in a cost effective manner. This paper proposes a vision based system to control various mouse activities such as left and right clicking using hand gestures to make the interaction more efficient and reliable.

FPGA based implementation of pulsed radar with time delay in digital beamforming using partially serial architecture

The Radars have been using the composition of digital and analog beamforming. In the analog beamforming at the output of phase shifters the sub-arrays are digitized. But such type of systems languishes with immured bandwidth and will not be capable to constitute concurrent beam. While in case of digital beamforming there are some assistance like broad bandwidth waveforms and concurrent beams at peculiar angles, frequencies and waveforms. These types of techniques were also costly in the previous years. But as per the presence of numerous multipliers in the field programmable gate arrays(FPGA) and converters it is in reach. In this paper, the implementation of fractional delay filter(FD) using partially serial architecture is done. It is further simulated with ISE using devices, SPARTAN-3ADSP and VIRTEX 5. In the end, the analogy of SPARTAN-3ADSP based XC3SD1800ACS484-4 device with VIRTEX 5 based XC5VLX50TFF1136-3 is shown. The result shows that the fractional delay filter on VIRTEX 5 is 128.94 times faster than SPARTAN-3ADSP.

FPGA based decimator using fully parallel technique for hearing aid applications

In this paper, implementation of a decimator using fully parallel technique for hearing aid applications is considered. A hearing aid is helpful for the people having hearing loss to hear more precisely in both quiet and whirring situations. It helps a person with hearing loss to listen and communicate by making sounds audible and clearer. The technique employed for the design of the filter is Canonic Signed Digit (CSD) representation. The higher sampling rate of the signal is decimated to low sampling rate by implementing the filter using the multirate approach. The main aim of the paper is to analyze and simulate the decimation filter using MATLAB. It is then simulated with ISE and finally implemented on FPGA devices. The two FPGA devices used are Spartan-3E and Virtex 2Pro. The comparison is done on two filter structures, Direct-form FIR and Direct-Form Symmetric FIR, for hardware resource utilization and speed. The hardware result shows that the proposed decimation filter designed on Virtex 2P with Direct Form symmetric structure is 12.79% faster than that designed on Spartan3E. The designed FIR filter with symmetric structure designed on Virtex 2P displays effective utilization of area and better speed in comparison to the design with Direct-Form structure on Spartan-3E.

Power and delay analysis of CMOS multipliers using Vedic algorithm

This paper presents an effective Vedic algorithm called as Urdhva-Tiryyagbhyam Sutra implementation and design for multipliers using 45nm technology. Multiplier is one of the most important parts of almost all digital system hardware, so a high speed, reduced delay, reduced area and low power consumption multiplier design will results in effective digital system designs. Thus this paper present an effective design and implementation of a multiplier with high speed, reduced delays, less area and low power consumption using our ancient methodology of Vedic mathematics that is Urdhva-Tiryagbhyam Sutra. This implementation is done in 45nm technology using chip designing tool Cadence Virtuoso at backend. Implemented Multiplier consumes very low power because of its carry skip addition methodology, reduced hardware and reduced delays. A 2 Bit multiplier consumes a very low power 5.5489×10 −11 watt and delay of 1.924×10 −12 sec and 4 Bit multiplier consumes power of 0.0002854 watt and delay of 2.0873×10−7 sec.

Reducing computational cost of ECG signal using multirate signal processing

The aim of this paper is reducing the computational costs of ECG-signal processing as compare to former method of digital filtering. We use multi-rate signal processing methods for the separation of slow wave periodic components in the heart rhythm in real time mode. Multi-stage structure for down sampling is designed. The MATLAB simulation has been used to evaluate and compare the computational cost for proposed model and known approaches. Our goal is reducing the filter length and aliasing.