Ralph Kauffman

A 1/2.5 inch 8.1Mpixel CMOS Image Sensor for Digital Cameras

A 1/2.5 inch 8.1Mpixel CMOS image sensor with 1.75mum pixel pitch is designed to operate at 2.8V for digital still camera applications and down to 2.4V in mobile applications. The chip uses top and bottom multiple channels with a double-data-rate analog signal readout at a rate of 96Mpixels/s, which results in total 192Mpixels/s. With the analog gain set to 15.875 and a 12b ADC the noise floor falls as low as 3.8e-, yielding a pixel DR of 63.8dB

A highly manufacturable 110 nm EDRAM process with Al/sub 2/O/sub 3/ stack MIM capacitor for cost effective high density, high speed, low voltage ASIC memory applications

A highly manufacturable 110 nm Embedded DRAM technology with stack Al/sub 2/O/sub 3/ MIM capacitor has been demonstrated successfully for the first time. High-density DRAM core with 0.1 /spl mu/m/sup 2/ cell size and high performance logic circuits have been realized at the same time by separation of the gate pattern at memory cell and peripheral logic region. Low temperature BDL process, highly reliable Al/sub 2/O/sub 3/ MIM capacitors have been developed to control process temperature. DRAM cell performance has been improved by introducing tungsten wordline, CoSi/sub 2/ plug and tungsten bitline. 7 levels Cu and CVD-OSG low-k material have been implemented to satisfy the requirement of high performance logic circuits design.