Ralph Mader

Intra-Task Parallelism in Automotive Real-Time Systems

Many recent Engine Management Systems (EMSs) have multicore processors. This results in new challenges for the developers of those systems, as most of them are not familiar with multicore programming. Additionally, many of the EMSs have real-time requirements, which need to be met. This paper introduces embedded parallel design patterns (ePDPs), which help developers solving common problems encountered when trying to parallelize legacy code for EMSs or embedded devices. We present a novel ePDP called Supercore Pattern. It helps to reduce the overhead introduced from forking or joining control graphs. To show the effectiveness of this pattern we simulated and executed it on a real-world EMS and show that the pattern is able to reduce the response time of tasks with real-time requirements. This paper also presents concrete extensions to AUTOSAR, and EAST-ADL, to enable the modelling of the supercore pattern in automotive modelling standards.

Improving instruction accurate simulation for parallel automotive applications

High level simulation and modeling techniques have matured significantly over the last years and have become more and more important in practice, e.g., in the industrial hardware development and especially the automotive domain. Complex and detailed modeling requires a lot of time during preparation and execution, is quite error prone and thus, reduces the average time-to-market significantly. One popular approach to mitigate this problem is statistical modeling and simulation. In this paper, we focus on another high level simulation approach for determining accurate runtimes of applications using instruction accurate modeling and simulation. We extend the basic instruction accurate simulation technology from OVP using cache models in conjunction with a statistical cost function, which enables high precision runtime predictions with an significant improvement over the pure instruction accurate approach.