Ram Raghavan

Cell broadband engine architecture and its first implementation: a performance view

The Cell Broadband Engine™ (Cell/B.E.) processor is the first implementation of the Cell Broadband Engine Architecture (CBEA), developed jointly by Sony, Toshiba, and IBM. In addition to use of the Cell/B.E. processor in the Sony Computer Entertainment PLAYSTATION® 3 system, there is much interest in using it for workstations, media-rich electronics devices, and video and image processing systems. The Cell/B.E. processor includes one PowerPC® processor element (PPE) and eight synergistic processor elements (SPEs). The CBEA is designed to be well suited for a wide variety of programming models, and it allows for partitioning of work between the PPE and the eight SPEs. In this paper we show that the Cell/B.E. processor can outperform other modern processors by approximately an order of magnitude and by even more in some cases.

Reducing interference among vector accesses in interleaved memories

Memory interference occurs when two or more concurrent data requests are addressed to the same main memory bank. In vector superconductors, this problem is serious due to the periodic interaction among vectors accesses, and can significantly reduce memory bandwidth and overall system performance. Two techniques can be used to reduce the effects of memory interference. First, vector data can be placed in the main memory such that, when accessed concurrently, the vectors do not interfere with one another. Second, buffers can be used at the memory banks to hold conflicting requests and to allow vector streams to continue to access other banks. Conditions for arbitrary numbers of vector streams to access an interleaved memory system without conflict are derived. It is shown that when three or more vector streams must be accessed concurrently, vector data placement to avoid conflicts becomes increasingly difficult, and that bank buffers can be effective under these conditions in increasing the effective memory bandwidth. >

IBM POWER7 performance modeling, verification, and evaluation

In this paper, we describe the key performance enhancements in IBM POWER7® microarchitecture and its memory hierarchy, including performance modeling and verification methodology. We also describe the performance characteristics of server applications, including Standard Performance Evaluation Corporation (SPEC) central processing unit, SAP Sales and Distribution, SPECjbb, online transaction processing workloads, and high-performance computing applications running on POWER7 processor-based systems compared with other systems.

CoveT: a coverage tracker for collision events in system verification

Hardware escapes in complex ASIC designs are very costly to fix in terms of both money and time. It is therefore necessary for design bugs to be detected and removed as early as possible in the design cycle. One cost-effective way of debugging a design is to simulate a software model of the design. However it has been traditionally difficult to measure how much of the design has been verified and how much simulation is sufficient. In this paper we describe a coverage tool called CoveT that is currently in use for system verification within IBMs RS/6000 Division. The novel idea behind this tool is the area of focus chosen for coverage measurement, viz., concurrent occurrence of multiple events at a given unit that tend to stress the underlying state machines. Our tool is helping us to track the progress of system simulation, uncover areas that are insufficiently stressed, potentially expose complex bugs, and increase the effectiveness of simulation cycles.