Ramkrishan Maheshwari

Design of Neutral-Point Voltage Controller of a Three-Level NPC Inverter With Small DC-Link Capacitors

A neutral-point-clamped three-level inverter with small dc-link capacitors is presented in this paper. The inverter requires zero average neutral-point current for stable neutral-point voltage. The small dc-link capacitors may not maintain capacitor voltage balance, even with zero neutral-point current. This may happen due to nonlinearities present in the circuit. This requires a fast control of the neutral-point voltage. A simple carrier-based modulation strategy which allows modeling of the neutral-point voltage dynamics as a continuous function of power drawn from the inverter is proposed. This continuous model shows that the neutral-point current is proportional to the power drawn from the inverter, and it enables the use of a well-established classical control theory for the neutral-point voltage controller design. A simple proportional integral controller is designed for the neutral-point voltage control on the basis of the continuous model. The design method for optimum performance is discussed. The implementation of the proposed modulation strategy and the controller is very simple. The controller is implemented in a 7.5-kW induction machine-based drive with only 14 μF dc-link capacitors. Also, the experimental results show that fast and stable performance of the neutral-point voltage controller are achieved and thus verify the validity of the proposed control approach.

Modified Discontinuous PWM for Size Reduction of the Circulating Current Filter in Parallel Interleaved Converters

Parallel voltage-source converters (VSCs) require an inductive filter to suppress the circulating current. The size of this filter can be minimized by reducing either the maximum value of the flux linkage or the core losses. This paper presents a modified discontinuous pulsewidth modulation (DPWM) scheme to reduce the maximum value of the flux linkage and the core losses in the circulating current filter. In the proposed PWM scheme, the dwell time of an active vector is divided within a half-carrier cycle to ensure simultaneous occurrence of the same zero vectors in both VSCs. A function to decide the ratio of the dwell time of the divided active vector is also presented. The effect of the proposed PWM scheme on the maximum value of the flux linkage and the core losses is analyzed and compared with that of the space vector modulation and 60

An Active Damping Technique for Small DC-Link Capacitor Based Drive System

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Influences of Device and Circuit Mismatches on Paralleling Silicon Carbide MOSFETs

clamped DPWM schemes. The analytical expressions for the maximum value of the flux linkage are derived for each of these PWM schemes. In addition, the effect of the proposed PWM scheme on the line current ripple and the switching losses is also analyzed and compared. To verify the analysis, experimental results are presented, which prove the effectiveness of the proposed PWM scheme.

Enhanced DC-Link Capacitor Voltage Balancing Control of DC–AC Multilevel Multileg Converters

A small dc-link capacitor based drive system shows instability when it is operated with large input line inductance at operating points with high power. This paper presents a simple, new active damping technique that can stabilize effectively the drive system at unstable operating points, offering greatly reduced input line current total harmonic distortion. The proposed method requires only a first-order, high-pass filter with a gain. Active damping voltage terms, linked directly to the dc-link voltage ripple through gain units, are injected to the drive machine for stabilizing the operating points. The stabilizing effect of the active damping terms is demonstrated for an induction machine based drive system. The effects of the added damping terms on the machine current and dc-link voltage are analyzed in detail. A design recommendation for the proposed active damping terms is given. Experimental results verifying the effectiveness of the new active damping method are presented.

Neutral-point current modeling and control for Neutral-Point Clamped three-level converter drive with small DC-link capacitors

This paper addresses the influences of device and circuit mismatches on paralleling the silicon carbide (SiC) MOSFETs. Comprehensive theoretical analysis and experimental validation from paralleled discrete devices to paralleled dies in multichip power modules are first presented. Then, the influence of circuit mismatch on paralleling SiC MOSFETs is investigated and experimentally evaluated for the first time. It is found that the mismatch of the switching loop stray inductance can also lead to on-state current unbalance with inductive output current, in addition to the on-state resistance of the device. It further reveals that circuit mismatches and a current coupling among the paralleled dies exist in a SiC MOSFET multichip power module, which is critical for the transient current distribution in the power module. Thus, a power module layout with an auxiliary source connection is developed to reduce such a coupling effect. Finally, simulations and experimental tests are carried out to validate the analysis and effectiveness of the developed layout.

Overmodulation of n-Level Three-Leg DC - AC Diode-Clamped Converters With Comprehensive Capacitor Voltage Balance

This paper presents a capacitor voltage balancing control applicable to any multilevel dc-ac converter formed by a single set of series-connected capacitors implementing the dc link and semiconductor devices, such as the diode-clamped topology. The control is defined for any number of dc-link voltage levels and converter legs (for single-phase and multiphase systems), guaranteeing the capacitor voltage control for any modulation index value and load (from idle mode to full power). The associated control loop small-signal transfer function is presented, from which optimum compensator design guidelines are derived. The improvement in control performance is verified through simulation and experiments comparing with a previous balancing control strategy in a four-level three-phase dc-ac conversion system. The satisfactory control performance is also verified through simulation in a four-level five-phase dc-ac conversion system.

Parallel interleaved VSCs: Influence of the PWM scheme on the design of the coupled inductor

A Neutral-Point-Clamped (NPC) three-level inverter with small DC-link capacitors is presented in this paper. This inverter requires zero average neutral-point current for stable neutral-point potential. A simple carrier based modulation strategy is proposed for achieving zero average neutral-point current. A new simplified model of the neutral-point voltage dynamics is derived for the proposed modulation strategy. This model shows that the neutral-point current is proportional to the power drawn from the converter and it enables the use of well established classical control theory for neutral-point voltage controller design. A PI controller is used for neutral-point voltage balance. The implementation of the proposed modulation strategy and controller is simple. It does not require any information about the output phase currents. The controller is implemented in a 7.5 kW induction machine based drive with only 14 µF DC-link capacitors. A fast and stable performance of the neutral-point voltage controller is achieved and verified by experiments.

Closed loop control of active damped small DC-link capacitor based drive

This paper presents a novel pulsewidth modulation (PWM) strategy for n-level three-leg semiconductor-clamped dc-ac converters in the overmodulation region, with dc-link capacitor voltage balance in every switching cycle. The strategy is based on the virtual-vector concept. Suitable reference vector trajectories are selected to obtain low weighted total harmonic distortion and a simple algorithm. A hexagonal-boundary compression factor is introduced to guarantee, at any operating point, dc-link capacitor voltage regulation capabilities in every switching cycle and avoid narrow gate pulses. The detailed PWM algorithm for an easy implementation in a digital control platform is also presented. The good performance of the strategy is verified through both simulation and experiments in a three-level three-phase neutral-point clamped converter.

Active damping technique for small DC-link capacitor based drive system

The line current ripple and the size of the dc-link capacitor can be reduced by interleaving the carriers of the parallel connected Voltage Source Converters (VSCs). However, the interleaving of the carriers gives rise to the circulating current between the VSCs, and it should be suppressed. To limit the circulating current, magnetic coupling between the interleaved legs of the corresponding phase is provided by means of a Coupled Inductor (CI). The design of the CI is strongly influenced by the Pulsewidth Modulation (PWM) scheme used. The analytical model to evaluate the flux-linkage in the CI is presented in this paper. The maximum flux density and the core losses, being the most important parameters for the CI design, are evaluated for continuous PWM and discontinuous pulsewidth modulation (DPWM) schemes. The effect of these PWM schemes on the design of the CI is discussed. The simulation and the experimental results are finally presented to validate the analysis.