Ramon Beivide

A PERFORMANCE EVALUATION OF ADAPTIVE ROUTING IN BIDIMENSIONAL CUT-THROUGH NETWORKS

The performance of the communication network of a massively parallel processor depends, among other parameters, on the network topology, the message flow control and the routing mechanisms. This paper analyses the gains in average message latency and maximum sustained throughput that can be achieved using an adaptive routing strategy instead of an oblivious one. Two different bidimensional topologies have been studied, mesh and torus, using cut-through message flow control. First, we have simulated an ideal case in which there is no limit to the temporary storage capacity of the routing node. Then, a more realistic design, that implies the implementation of a deadlock avoidance technique, is analysed. To assure deadlock-free routing, the network is split into several virtual networks. Results show that adaptive routing is not a good election with this kind of networks. The torus topology shows potentially better results than the mesh. In any case, a different deadlock avoidance technique should be implemented if these potential gains are to be exploited.

Parallel simulation of message routing networks

An implementation of a conservative parallel simulator with deadlock avoidance is presented. Its performance when working with a realistic model of a message routing network is evaluated and contrasted against a sequential simulator. Different factors that improve the performance of the parallel simulation are discussed, focusing in the model under study and the available computer: a network of transputers. These factors are the load of the model being simulated, the grain size of the simulator and the simulator ability to exploit the lookahead property of the model.<<ETX>>

Impact of the Head-of-Line Blocking on Parallel Computer Networks: Hardware to Applications

A fully adaptive router with hybrid buffers at the input and output channels was designed, which improves the throughput of its input buffer counterpart by up to 40% and has only 10% higher base latency. An in-depth analysis of different router buffer organization was carried out for a toroidal network, which uses either a deterministic (DOR) or a fully adaptive routing scheme. Each proposal is described in VHDL and evaluated with the Synopsys synthesis tool. Technological restrictions obtained were used to evaluate network performance under both synthetic loads and real applications.

An empirical evaluation of techniques for parallel discrete-event simulation of interconnnection networks

Three parallel discrete-event simulators-synchronous, conservative and optimistic-implemented on an Intel Paragon multicomputer are comparatively evaluated. Parallelism is achieved by model decomposition, distributing the simulation among a set of collaborative logical processes. The three simulators differ in the way those processes synchronize to obey causal restrictions in the simulation of events. Message passing network models are used to study these simulation alternatives. A set of experiments are carried out to understand how model parameters influence simulator performance. Experimental evidence leads to the conclusion that the optimistic simulator is not a viable tool for the analysis of this kind of models. The opposite conclusion applies to the other two: if the workload assigned to each logical process is above a certain threshold then the synchronization overhead is comparatively low and the simulators perform and scale well up to a large number of processors. The performance threshold is influenced by some parameters of the simulated model (size of the network, load level and message length), as well as by the number of processors used by the simulators.

Packet multiplexing: an efficient router implementation for adaptive mesh networks

The performance of an interconnection network with adaptive routing is strongly related to the deadlock avoidance method it applies. Virtual channels are normally used for this purpose in mesh and torus networks. This work compares true architectural alternatives in the router design: mapping each virtual channel onto a different physical link and multiplexing the set of virtual channels onto the same physical link. Besides, multiplexing at the packet level is proposed as an alternative to multiplexing at the flit level, showing the advantages of this not previously used approach. The benefits of each multiplexing type, both in message latency and throughput, have been evaluated under several traffic conditions. An estimation of the node delay for each implementation scheme has also been calculated.<<ETX>>