Ramyanshu Datta

On-chip delay measurement for silicon debug

Efficient test and debug techniques are indispensable for performance characterization of large complex integrated circuits in deep-submicron and nanometer technologies. Performance characterization of such chips requires on-chip hardware and efficient debug schemes in order to reduce time to market and ensure shipping of chips with lower defect levels. In this paper we present an on-chip scheme for delay fault detection and performance characterization. The proposed technique allows for accurate measurement of delays of speed paths for speed binning and facilitates a systematic and efficient test and debug scheme for delay faults. The area overhead associated with the proposed technique is very low.

Delay fault testing and silicon debug using scan chains

This paper describes a novel technique to reuse the existing scanpaths in a chip for delay fault testing and silicon debug. Efficient test and debug techniques for VLSI chips are indispensable in Deep Submicron technologies. A systematic debug scheme is also necessary in order to reduce time-to-market. Due to stringent timing requirements of modern chips, test and debug schemes have to be tailored for detection and debug of functional defects as well as delay faults quickly and efficiently. The proposed technique facilitates an efficient scheme for detecting and debugging delay faults and has minimal area and power overhead.

A scheme for on-chip timing characterization

We present a novel technique for performing post-silicon timing characterization, i.e., delay fault test and debug, using on-chip delay measurement of critical paths in Integrated Circuits. In Deep Submicron technologies, timing related failures have become a major source of defective silicon, making it imperative to carry out efficient delay fault testing on such chips. In addition to test, there is also a need for an efficient and systematic silicon debug methodology for timing related failures. Existing timing characterization strategies are not effective in Deep Submicron technologies due to limitations on controllability and observability. The proposed technique uses a novel scheme to perform on-chip delay measurement and thus facilitate quick and efficient testing and debugging of delay faults in chips. The scheme has minimal hardware overhead and is robust in face of process variations.

Tri-scan: a novel DFT technique for CMOS path delay fault testing

We propose a novel design for testability technique to apply two pattern tests for path delay fault testing. Due to stringent timing requirements of deep-submicron VLSI chips, design-for-test schemes have to be tailored for detecting stuck-at as well as delay faults quickly and efficiently. Existing techniques such as enhanced scan add substantial hardware overhead, whereas techniques such as scan-shifting or functional justification make the test generation process complex and produce lower coverage for scan based designs as compared to non-scan designs. We exploit the characteristics of CMOS circuitry to enable the application of two-pattern tests. The proposed technique reduces the problem of path delay fault testing for scan based designs to that of path delay fault testing with complete accessibility to the combinational logic, and has minimal area overhead. The scheme also provides significant reduction in power during scan operation.

Adaptive Design for Performance-Optimized Robustness

We present adaptive design techniques that compensate for manufacturing induced process variations in deep sub-micron (DSM) integrated circuits. Process variations have a significant impact on parametric behavior of modern chips, and adaptive design techniques that make a chip self-configuring to work optimally across process corners are fast evolving as a potential solution to this problem. Such schemes have two main components, a mechanism for sensing process perturbations, and one or more process compensation schemes that are driven by this mechanism. The adaptive design schemes presented in this paper are simple, low overhead techniques for noise tolerance in DSM CMOS circuits, to enhance their manufacturing yield. The process perturbation sensing scheme is based on on-chip delay measurement with a performance based bound on adaptation, which enables performance optimized robustness to noise in the face of process variations

On-Chip Delay Measurement Based Response Analysis for Timing Characterization

We present techniques for response analysis for timing characterization, i.e., delay test and debug of Integrated Circuits (ICs), using on-chip delay measurement of critical paths of the IC. Delay fault are a major source of failure in modern ICs designed in Deep Sub-micron technologies, making it imperative to perform delay fault testing on such ICs. Delay fault testing schemes should enable detection of gross as well as small delay faults in such ICs to be efficient. Additionally there is a need for performing efficient and systematic silicon debug for timing related failures. The timing characterization techniques presented in this paper overcome the observability limitations of existing timing characterization schemes in achieving the aforementioned goals, thus enabling quick and efficient timing characterization of DSM ICs. Additionally the schemes have low hardware overhead and are robust in face of process variations.

Testing and debugging delay faults in dynamic circuits

We propose novel design for test and debug techniques to apply two patterns for delay fault test and debug in dynamic circuits. Dynamic circuits, which have traditionally been difficult to test, pose new challenges for AC tests due to the presence of a reset phase between applications of any two patterns, which impedes delay fault testing of such circuits. We present two sets of design for test and debug techniques. The first set facilitates application of two patterns to dynamic circuits in general, overcoming the issue of reset phase, and reduces the problem of test generation for dynamic circuits to test generation for pull down paths of static CMOS circuits. The second set enables application of two patterns to scan based dynamic circuits. The proposed techniques reduce the problem of delay test generation for scan based dynamic circuits to that of delay test generation for static CMOS circuits with complete accessibility to all primary inputs. The techniques have minimal area overhead and also provide significant reduction in power during scan operation

Design of Shifting and Permutation Units using LSDL Circuit Family

Migration of designs into a smaller technology node, that traditionally resulted in an increase in performance, is yielding reduced returns as we scale into the sub-90 nm domain. This has made it imperative to explore alternative methods like improvements in circuit design to sustain growth in performance of Integrated Circuits. The Limited switching dynamic logic (LSDL) circuit family has been suggested as an efficient and high performance circuit design technique to overcome the problem of stagnating performance. In this paper, we present case studies in design of arithmetic units using LSDL selector circuits. The first unit we present is a shifter, with the added novelty that it can provide the shifted data in complemented or non-complemented form without requiring an additional module for performing the negate operation. The second unit is a permute unit, used to line up data in media units using a single instruction, so that the media unit can operate on the data. However, existing permute units have a severe limitation in that they can move only discrete immutable bytes. Our module overcomes this by enabling extraction of any set of eight consecutive bits in a data stream, thus providing bit-level granularity in the permute operation, without altering the format of the existing permute instruction.

A low latency and low power dynamic Carry Save Adder

This paper presents a 4-to-2 Carry Save Adder (CSA) using dynamic logic and the Limited Switch Dynamic Logic (LSDL) circuit family. Adders are a crucial portion of all floating-point units, since they form the base element of all arithmetic functions. The 4-to-2 circuits reported previously do not meet the requirements of the next generation of processors. The adder presented here is built using a dynamic circuit style that improves performance significantly. Further a latching element after each dynamic evaluation node controls the power of the dynamic circuits. In this paper we project some of the salient features of the LSDL circuit family by comparing this 4-2 circuit with the most similar static implementation. Use of the LSDL circuit family displays significant improvement not only in terms of performance but also with respect to power dissipation, leakage and area.

Controllability of Static CMOS Circuits for Timing Characterization

Timing violations, also known as delay faults, are a major source of defective silicon in modern Integrated Circuits (ICs), designed in Deep Sub-micron (DSM) technologies, making it imperative to perform delay fault testing in these ICs. However, DSM ICs, also suffer from limited controllability and observability, which impedes easy and efficient testing for such ICs. In this paper, we present a novel Design for Testability (DFT) scheme to enhance controllability for delay fault testing. Existing DFT techniques for delay fault testing either have very high overhead, or increase the complexity of test generation significantly. The DFT technique presented in this paper, exploits the characteristics of CMOS circuit family and reduces the problem of delay fault testing of scan based sequential static CMOS circuits to delay fault testing of combinational circuits with complete access to all inputs. The scheme has low overhead, and also provides significant reduction in power dissipation during scan operation.