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Featured researches published by Ran Cheng.


Applied Physics Letters | 2016

Demonstration of ultra-thin buried oxide germanium-on-insulator MOSFETs by direct wafer bonding and polishing techniques

Zejie Zheng; Xiao Yu; Min Xie; Ran Cheng; Rui Zhang; Yi Zhao

The ultra-thin body and ultra-thin buried-oxide (UTBB) Germanium-on-Insulator (GeOI) substrates have been fabricated by direct wafer bonding and polishing techniques. The Ge and BOX layer thicknesses are as thin as 9 and 13 nm, respectively. The UTBB GeOI substrates exhibit superior crystal quality (similar to the bulk single crystalline Ge) and sufficiently reduced surface roughness. As a result, the Hall hole mobility of UTBB GeOI reaches 1330 cm2/V s with a carrier concentration of 2 × 1016 cm−3. The inversion mode UTBB GeOI nMOSFETs have also been demonstrated with suppressed mobility degradation during Ge layer thinning, indicating the feasibility of this GeOI substrate formation technique in future CMOS technologies.


international reliability physics symposium | 2017

Ultrafast pulse characterization of hot carrier injection effects on ballistic carrier transport for sub-100 nm MOSFETs

Ran Cheng; Xiao Yu; Lei Shen; Longxiang Yin; Yanyan Zhang; Zejie Zheng; Bing Chen; Xiaohui Liu; Yi Zhao

In this work, we investigate the effect of hot carrier injection (HCI) on the ballistic transport characteristics of SOI MOSFETs for the first time. Ballistic efficiency is an important indicator of device performance for nanoscale transistors. In the process of HCI stress, the traps and defects generated in the transistor channel would increase the carrier scattering and therefore degrade the ballistic efficiency. The effect of this degradation changes with gate length. In addition, due to low thermal conductivity of the oxide layer and high on-state current for nanoscale transistors, the SOI MOSFETs suffer from severe self-heating effect (SHE) which would affect the accurate evaluation of HCI effects on the ballistic carrier transport. Ultrafast pulse measurement were employed in this study to exempt the SHE from the characterization process, yielding more realistic results for the reliability estimation on device ballisticity.


ieee international conference on solid state and integrated circuit technology | 2016

A systematic study on dry etching process of germanium for Ge 3D-FETs applications

Yanyan Zhang; Ran Cheng; Shun Xu; Rui Zhang; Yi Zhao

In this study, reactive-ion etching (RIE) of Ge in different ambient was systematically investigated. Several dominant parameters (applied power, gas flow rate and gas compositions) during the etching were considered to improve the profile of 3D Ge structures. Besides, it was experimentally confirmed that to obtain Ge sidewalls with small roughness and a large angle, adding O2 and an appropriate masking material are important. Finally, by optimizing the process parameters, Ge sidewalls with an angle near 80° and smooth surfaces were successfully achieved.


IEEE Electron Device Letters | 2017

Experimental Investigation of Ballistic Carrier Transport for Sub-100-nm Ge n-MOSFETs

Ran Cheng; Longxiang Yin; Heng Wu; Xiao Yu; Yanyan Zhang; Zejie Zheng; Wangran Wu; Bing Chen; Peide D. Ye; Xiaohui Liu; Yi Zhao


international reliability physics symposium | 2018

Effect of measurement speed (μs-800 ps) on the characterization of reliability behaviors for FDSOI nMOSFETs

Yiming Qu; Ran Cheng; Wei Liu; Junkang Li; Bich-Yen Nguyen; O. Faynot; Nuo Xu; Bing Chen; Yi Zhao


IEEE Transactions on Electron Devices | 2018

High-Source-Drain Voltage-Induced Reliability Issues of Sub-28-nm Node MOSFET's Application in Resistive-Type Nonvolatile Memory Array

Bing Chen; Ran Cheng; Yi Zhao


IEEE Transactions on Electron Devices | 2018

Back-Gate Modulation in UTB GeOI pMOSFETs With Advanced Substrate Fabrication Technique

Zejie Zheng; Xiao Yu; Yanyan Zhang; Min Xie; Ran Cheng; Yi Zhao


IEEE Transactions on Electron Devices | 2018

Quantitative Characterization of Fast-Trap Behaviors in Al 2 O 3 /GeO x /Ge pMOSFETs

Xiao Yu; Ran Cheng; Jiabao Sun; Yiming Qu; Jinghui Han; Bing Chen; Yi Zhao


IEEE Electron Device Letters | 2018

Ge-Based Asymmetric RRAM Enable

Bing Chen; Yi Zhang; Wei Liu; Shun Xu; Ran Cheng; Rui Zhang; Yi Zhao


IEEE Electron Device Letters | 2018

8{F}^{2}

Zejie Zheng; Ran Cheng; Yiming Qu; Xiao Yu; Wei Liu; Zhuo Chen; Bing Chen; Qing-Qing Sun; David Wei Zhang; Yi Zhao

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