Rana Ejaz Ahmed

Software maintenance outsourcing: Issues and strategies

Abstract Software maintenance outsourcing is becoming a popular alternative in software industry. Software companies are looking at outsourcing their maintenance and support activities as an area for competitive advantage. There are risks and benefits of introducing subcontractors in the framework of software outsourcing. Reliable maintenance is only possible if adequate measures are taken in advance during project’s development and maintenance planning phase and are documented in the maintenance contract. In this paper, we present and make a justification for a set of recommendations to make such maintenance reliable and cost-effective. We analyze the associated risks and propose some product quality metrics to be monitored during the maintenance phase.

Energy-Aware Cache Coherence Protocol for Chip-Multiprocessors

Chip-multiprocessors (CMs) are gaining popularity for future microprocessors to be used in high-end systems (e.g., server machines) as well as in the low-power systems (e.g., mobile devices, laptops). The CM system consists of several processors cores connected to their respective L1 caches via a bus, and a common L2 cache. The design of a cache coherence protocol in CM presents unique challenges when the power consumption is as important an issue as the overall performance. This paper presents a new energy-aware cache coherence protocol for CMs that minimizes the snoop traffic. The paper shows that a tradeoff exists between the cache performance and the power saving in the cache system, in general. The system uses L1 cache to store only the instructions for the related processor while L2 cache stores both the instructions and the data. The paper presents an analytical model for power estimation and average memory access time. Several results under various parameter changes are presented and trade-offs are highlighted. The results of the proposed protocol are also compared with some existing snoopy cache coherence protocols

VLSI architecture for computing third-order cumulants

The higher order statistics (HOS) (or cumulants), and their associated Fourier Transforms, have been established as a powerful analytical tool in modern signal processing. This paper presents a computationally efficient VLSI architecture for computing third-order cumulants. The architecture is based on the systolic array implementation and exploits parallelism, pipelining, and regular cell structures. The architecture is designed with 10μm CMOS technology using the scalable design rules of MOS Integrated Services (MOSIS). The VLSI architecture contains approximately 36 500 transistors and it is capable of operating at a speed of 5-2 MHz.

New job selection and location policies for load-distributing algorithms

This paper presents a new distributing algorithm that uses new job selection and location policies. The algorithm is shown to outperform the best-reported load distributing algorithms.

A Methodology for Network Topology Design with Link and Node Failures Tolerance

This article describes a new methodology for network topology design considering the problems of single link-failure and single node-failure tolerances.

A fault-tolerant, energy-efficient routing protocol for wireless sensor networks

Multi-hop Wireless Sensors Networks (WSNs) consisting of several nodes and links are vulnerable to frequent node/ link failures. Energy saving at a node is another major consideration in WSN. Dynamic Source Routing (DSR) is a popular protocol commonly applied to WSNs; however, there is no provision of fault-tolerance and energy efficiency. In this paper, a new fault-tolerant routing and energy-efficient protocol, that modifies the conventional DSR protocol, is proposed. The protocol tries to find two routing paths (if they exist) from the source to the destination node, considering the present energy levels at intermediate nodes in the path. Simulation results show that the proposed protocol also achieves better packet delivery ratio and network throughput as compared to conventional DSR.

Directory-based cache coherence protocol for power-aware chip-multiprocessors

Multi-core processor architectures, also known as chip-multiprocessors (CMPs), have become a predominant technology for applications demanding both the high bandwidth and the low power. A typical CMP architecture integrates multiple processor cores, one or more memory controllers, a multi-level cache hierarchy, and an interconnection network on a single chip. Sharing of large size cache among multi-cores poses a number of new challenges to be addressed in terms of cache-coherence and power management. This paper investigates the integration of a directory-based cache coherence protocols for the last level shared cache (L2/L3) for power-aware CMP architectures. We propose a scalable directory-based cache coherence protocol with minimal hardware overhead. The protocol supports the “sleep” mode for one or more cores without running into issues of data inconsistencies of shared data. The paper also presents the framework of an analytical model to evaluate the performance of the proposed protocol.

VLSI architecture for HDTV sub-band coding using GQMFs' filterbanks

A VLSI architecture for a low complexity intraframe subband image coding for HDTV signals is presented. The generalized quadrature mirror filters (GQMFs), which have smaller overall delay, are optimized in order to achieve high coding efficiency. The filter design exploits a symmetry property among different filter coefficients which, in turn, reduces the hardware complexity of the VLSI architecture substantially. The architecture is designed with 1 /spl mu/m CMOS technology using the scalable design rules of MDS Integrated Services Inc. (MOSIS). The VLSI architecture contains approximately 200,000 transistors and it is capable of operating at a speed of 34 MHz. The HDTV signals are decomposed into seven bands. The baseband is DPCM encoded and the high bands are PCM encoded. It is shown that high quality HDTV images can be obtained at a low bit rate as 0.654 bpp (bits/pixel). >

On fairness in LTE downlink MAC scheduling algorithms

A downlink MAC scheduler aims to improve the radio resources utilization in the Long Term Evolution (LTE) network. The MAC scheduler is responsible for sharing the available radio Resource Blocks (RBs) among different User Equipment (UEs) in time and frequency domains. Several downlink MAC schedulers have been proposed and implemented; however, providing fairness in terms of granting resources to different UEs with different QoS requirements remains a challenge. This paper presents the results of a comparative simulation study with respect to a fairness criterion for three well-known downlink schedulers.

Energy-aware QoS uplink scheduling for UGS traffic services in WiMAX

This paper presents new energy-aware QoS scheduling and call admission control algorithms for WiMAX IEEE 802.16e broadband wireless access standard. The scheduling algorithm works at MAC layer and is designed towards minimizing power consumption at mobile stations supporting multiple UGS connections, while meeting the QoS requirements of the connections. The scheduling algorithm uses a novel idea to fill an active OFDM frame as much as possible in order to increase the number of OFDM frames in sleep mode at mobile station. The algorithm also considers the dynamic nature of connection joining and termination, and the schedule adjusts itself on a new connection arrival. We used VoIP traffic connection models to simulate and validate our algorithms. Simulation results show that a power saving in the range of 50–75% can be easily achieved at the mobile station under low-to-moderate traffic intensities.