Ranjani Parthasarathi

Practical and scalable evolution of digital circuits

This paper addresses the scalability problem prevalent in the evolutionary design of digital circuits and shows that Evolvable Hardware (EHW) can indeed be considered as a viable alternative design methodology for large and complex circuits. Despite the effort by the EHW community to overcome the scalability problems using both direct mapped techniques and developmental approaches, so far only small circuits have been evolved. This paper shows that, by partitioning a digital circuit and making use of a modular developmental approach, namely, the Modular Developmental Cartesian Genetic Programming (MDCGP) technique, it is indeed possible to evolve large circuits. As a proof of concept, a 5x5 multiplier is evolved for partition sizes of 32 and 64. It is shown that compared to the direct evolution technique, the MDCGP technique provides five times reduction in terms of evolution times, 6-56% reduction in area and improved fault tolerance. The technique is readily scalable and can be applied to even larger partition sizes, and also to sequential circuits, thus providing a promising path to evolve large and complex circuits.

Trace Based Mobility Model for Ad Hoc Networks

Mobility of the nodes in a mobile ad hoc network poses a challenge in determining stable routes in the network. It is often difficult to predict the mobility of the nodes, as they tend to be random in nature. However, a non-random component would also exist in many scenarios. It is this non-random behavior that we consider in this paper to identify the movement trace of the mobile nodes. An algorithm is proposed to model the regular movement of a node as a trace containing a list of stable positions and their associated time. We call this model as a trace based mobility model (TBMM). The effectiveness of this model is shown by predicting the accuracy of a node movement by performing a ten fold cross validation. We also show the applicability of the trace information in the routing protocol to provide quality of service (QoS).

A Graph Based Query Focused Multi-Document Summarization

A users information need, normally represented as a search query, can be satisfied by creating a query focused coherent and readable summary, by fusing the relevant parts of information from multiple documents. While aggregating the information from multiple documents, the quality of the summary is improved by eliminating redundant information from the document set. In this paper, we focus on removing such redundant information and identifying the essential components from multiple documents (represented as a single global semantic graph), with respect to the given query (represented as a query graph). While the redundancy elimination is carried out using various levels of graph matching which are then indicated through canonical labeling of graphs, the selection of essential components for a query focused summary is performed, through the modified spreading activation theory, where the query graph is also integrated during the spreading activation over the global graph. The proposed system shows significant improvements in generating summaries when compared to other existing summarization systems.

Enhancing the development based evolution of digital circuits

The problem of scale has left the Evolvable Hardware (EHW) community wondering about the viability of this approach as an alternative design methodology for large and practical circuits. Despite the move from conventional direct mapped techniques to developmental approaches, so far only small circuits have been evolved. This paper shows that, by partitioning a digital circuit and making use of a developmental approach, namely the Developmental Cartesian Genetic Programming (DCGP) technique, it is possible to evolve large circuits. The advantages of this approach with respect to evolution time, area overhead and fault tolerance are highlighted for different adder and multiplier circuits and the ISCAS¿89-benchmark circuit rd84. This concept can be easily extended to any combinational circuit, thus proving that this is a viable solution towards evolving large and complex circuits.

An intelligent task analysis approach for special education based on MIRA

Abstract This paper describes a novel approach for generating a logical sequence of tasks in the task analysis process of special education. This approach is based on the formalism MIRA (Mīmāṁsā Inspired Representation of Actions), which has the feature of expressing an action as reason, instruction and goal. MIRA also prescribes a set of deduction rules, which helps in the reasoning process of actions. These features are incorporated in this approach and a software tool, namely MIRATaskGen is designed, which facilitates the task analysis process of special education. The software receives various action related inputs along with the start and finish stages and generates a sequence of tasks from the start to the finish. This tool also informs the user, whether the desired goal can be achieved. If the desired goal cannot be achieved, then the sequence of actions from the start to a point of discontinuity is detected.

An active framework for a WLAN access point using intel's IXP1200 network processor

Active Networks provide the user with the capability to inject customized programs into the network The network nodes should interpret these programs and perform the desired operation on the data flowing through the network The Network Processor (NP), a special purpose programmable device designed specifically to process packets at high speed with its concurrent packet processing model, forms an ideal platform for the implementation of active networks This paper presents the development of an active framework using the IXP1200 network processor This active framework is implemented for a Wireless LAN Access Point that bridges wired and wireless network segments This framework allows the access point to use different classification, scheduling or queue management algorithms for different applications The special features of IXP1200 such as multiprocessing, multithreading, block data movement, etc., are exploited to develop the access point and the active framework, with increased processing speed, scalability and flexibility.

Abstractive Summarization: A Hybrid Approach for the Compression of Semantic Graphs

Customization of information from web documents is an immense job that involves mainly the shortening of original texts. This task is carried out using summarization techniques. In general, an automatically generated summary is of two types-extractive and abstractive. Extractive methods use surface level and statistical features for the selection of important sentences, without considering the meaning conveyed by those sentences. In contrast, abstractive methods need a formal semantic representation, where the selection of important components and the rephrasing of the selected components are carried out using the semantic features associated with the words as well as the context. Furthermore, a deep linguistic analysis is needed for generating summaries. However, the bottleneck behind abstractive summarization is that it requires semantic representation, inference rules and natural language generation. In this paper, The authors propose a semi-supervised bootstrapping approach for the identification of important components for abstractive summarization. The input to the proposed approach is a fully connected semantic graph of a document, where the semantic graphs are constructed for sentences, which are then connected by synonym concepts and co-referring entities to form a complete semantic graph. The direction of the traversal of nodes is determined by a modified spreading activation algorithm, where the importance of the nodes and edges are decided, based on the node and its connected edges under consideration. Summary obtained using the proposed approach is compared with extractive and template based summaries, and also evaluated using ROUGE scores.

A deconverter framework for Malayalam

This paper discusses the design and implementation of a deconverter framework for the Malayalam Language. The Universal Networking Language or UNL facilitates translation between Natural Languages across the world. The paper focuses on the linguistic aspects of Malayalam required for the deconversion process. The case marking module handles the different UNL relations and their corresponding language features in Malayalam. A Morphological Generator takes care of generation of Malayalam words with the appropriate case endings and features, with respect to the cases and UNL attributes present in the UNL expression. The words are rearranged by the Syntax Planning Module to produce proper Natural Language sentences. These language dependent features for Malayalam have been successfully incorporated into a Deconverter Framework that handles English and Tamil currently. The Deconverter for Malayalam can currently produce simple Malayalam sentences and handle sentences with single clausal phrases also. It is being enhanced to handle more types of sentences. The present system is a small achievement towards attaining a complete translation facility for the Malayalam language. The following sections examine what has been implemented so far in the Deconverter and what more can be done to realize that dream of a translation facility.

Secure communication for multipath ad hoc network

A mobile ad hoc network is a collection of wireless mobile nodes that are capable of communicating with each other without the use of network infrastructure or any centralized administration. One main challenge in the design of these networks is their vulnerability to security attacks. In this paper, the security challenges in ad hoc networks are analyzed and secure communication is explored using the characteristics provided in an ad hoc network. In particular, the inherent redundancy in an ad hoc network is used to exchange secret keys. A secure DSR protocol is proposed in which the DSR [David B. Johnson et al., February 2002] routing protocol is enhanced with a security mechanism to send data in an encrypted format. The secret keys are exchanged without any centralized party or key management scheme. Using the DSR routing protocol and the Diffie-Hellman [W. Diffie et al., November 1976] key exchange method, secure communication is obtained with less effort, without any performance degradation.

Live-Cache: Exploiting Data Redundancy to Reduce Leakage Energy in a Cache Subsystem

Large on-chip caches can significantly improve the processor performance. But, they also increase the on-chip energy spent. With the increase in transistor density and decrease in feature sizes, the dominant component of the energy spent is the leakage energy. Since, on-chip caches consume a major portion of the chip’s transistor budget, they are good candidates for the control of leakage energy. In the cache hierarchy, most of the time, the data present at the first level also exists in the lower levels, and hence expends the leakage energy in all the levels that it is present. This paper proposes a mechanism to reduce this leakage energy by exposing the redundancy. In this mechnism, sub-blocks of the L1-data cache are turned off, when the data also exists in the register file. Also, a control mechanism is proposed to turn-off the blocks of L2-cache (in both instruction cache and data cache portions) when the data also exists in L1-cache. An architectural technique is also proposed, to effectively turn-off the portions of the L1 and L2-caches, which are never used for data storage by keeping the cache circuitry initially in low-leakage mode. The effectiveness of the proposed schemes has been demonstrated through cycle accurate simulation using a set of media and SPEC CPU 2000 benchamrks. This mechanism yields an average of about 33% to 36% reduction in the leakage energy for 16 KB to 32 KB dl1-cache and an average of 79% and 86% for 128 KB of dL2 and iL2 caches respectively, albeit with a little performance degradation.