Ranjith Kumar

Reversed Temperature-Dependent Propagation Delay Characteristics in Nanometer CMOS Circuits

The supply voltage to threshold voltage ratio is reduced with each new technology generation. The gate overdrive variation with temperature plays an increasingly important role in determining the speed characteristics of CMOS integrated circuits. The temperature-dependent propagation delay characteristics, as shown in this brief, will experience a complete reversal in the near future. Contrary to the older technology generations, the speed of circuits in a 45-nm CMOS technology is enhanced when the temperature is increased at the nominal supply voltage. Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable operation under temperature fluctuations. A design methodology based on optimizing the supply voltage for temperature-variation-insensitive circuit performance is proposed in this brief. The optimum supply voltage is 45% to 53% lower than the nominal supply voltage in a 180-nm CMOS technology. Alternatively, the optimum supply voltage is 15% to 35% higher than the nominal supply voltage in a 45-nm CMOS technology. The speed and energy tradeoffs in the supply voltage optimization technique are also presented

Impact of temperature fluctuations on circuit characteristics in 180nm and 65nm CMOS technologies

Temperature fluctuations alter threshold voltage, carrier mobility, and saturation velocity of a MOSFET. Temperature fluctuation induced variations in individual device parameters have unique effects on MOSFET drain current. Device parameters that characterize the variations in MOSFET current due to temperature fluctuations are identified in this paper for 180 nm and 65nm CMOS technologies. Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable circuit operation under temperature variations. A design methodology based on optimizing the supply voltage for temperature variation insensitive circuit performance is presented. Circuits display a temperature variation insensitive behavior when operated at a supply voltage 45% to 53% lower than the nominal supply voltage in a 180 nm CMOS technology. Similarly, the optimum supply voltages are 68% to 69% lower than the nominal supply voltage for circuits in a 65nm CMOS technology. The optimum supply voltages are similar for a diverse set of circuits in both technologies. The proposed technique of operating large scale designs at an optimum supply voltage for diminishing the performance sensitivity to temperature fluctuations is demonstrated to be feasible

A design methodology for temperature variation insensitive low power circuits

Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable circuit operation under temperature fluctuations. A design methodology based on optimizing the supply voltage for temperature variation insensitive circuit performance is presented in this paper. Circuits display temperature variation insensitive delay characteristics when operated at a supply voltage 45% to 53% lower than the nominal supply voltage (VDD = 1.8V) in a 180nm CMOS technology. Integrated circuits operating at scaled supply voltages consume low power at the cost of reduced speed. The proposed design methodology of optimizing the supply voltage for temperature variation insensitive circuit performance is, therefore, particularly attractive in low power applications with relaxed speed requirements. The energy, delay, and energy-delay product (EDP) are compared at the supply voltages that yield temperature variation insensitive circuit performance and minimum energy-delay product. Results indicate that low-power integrated circuits can also be made insensitive to temperature fluctuations with a modest amount of increase in energy-delay product.

Temperature-Adaptive Energy Reduction for Ultra-Low Power-Supply-Voltage Subthreshold Logic Circuits

Circuits optimized for minimum energy consumption operate typically in the subthreshold regime with ultra-low power-supply-voltages. Speed of subthreshold logic circuits is enhanced with an increase in the die temperature. The excessive timing slack observed in the clock period of constant-frequency subthreshold logic circuits at elevated temperatures provides new opportunities to lower the active mode energy consumption. Temperature-adaptive dynamic supply voltage tuning technique is proposed in this paper to enhance the high temperature energy efficiency of ultra-low-voltage subthreshold logic circuits. Results indicate that the energy consumption of subthreshold logic circuits can be lowered by up to 40% by dynamically scaling the supply voltage without degrading the clock frequency at elevated temperatures.

Voltage optimization for temperature variation insensitive CMOS circuits

The supply voltage to threshold voltage ratio is reduced with each new technology generation. The gate overdrive variation with temperature plays an increasingly important role in determining the speed characteristics of CMOS integrated circuits. The temperature dependent propagation delay characteristics, as shown in this paper, will experience a complete reversal in the near future. Contrary to the older technology generations, the speed of circuits in a 45 nm CMOS technology is enhanced when the temperature is increased at the nominal supply voltage. Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable operation under temperature variations. A design methodology based on optimizing the supply voltage for temperature variation insensitive circuit performance is presented in this paper. The optimum supply voltage is 45% to 57% lower than the nominal supply voltage in a 180 nm CMOS technology. Alternatively, the optimum supply voltage is 10% to 54% higher than the nominal supply voltage in a 45 nm CMOS technology. The gap between the optimum and nominal supply voltages increases in a low-power design. Deeply scaled low-power integrated circuits operating at ultra-low voltage supplies are, therefore, expected to be highly sensitive to temperature variations. Alternatively, the speed-centric determination of the supply voltage will be less catastrophic for maintaining the circuit reliability under temperature variations in the future technology generations

Temperature Variation Insensitive Energy Efficient CMOS Circuits in a 65nm CMOS Technology

A design methodology based on optimizing the supply voltage for simultaneously achieving energy efficiency and temperature variation insensitive circuit performance is presented in this paper. Circuits exhibit temperature variation insensitive delay characteristics when operated at a supply voltage 67% to 68% lower than the nominal supply voltage. At scaled supply voltages, integrated circuits consume low power at the cost of reduced speed. The proposed design methodology of optimizing the supply voltage for temperature variation insensitive circuit performance is, therefore, particularly attractive for low power applications with relaxed speed requirements. The supply voltages that yield minimum energy and minimum energy-delay product are identified at two different temperatures for circuits in a 65 nm CMOS technology. The energy and speed at the supply voltages providing temperature variation insensitive propagation delay, minimum energy, and minimum energy-delay product are compared. Results indicate that energy efficient integrated circuits with deeply scaled supply voltages can also be made insensitive to temperature fluctuations by considering the temperature dependence of speed in the supply voltage optimization process.

Temperature-adaptive body-bias and supply voltage scaling for enhanced energy efficiency in nano-CMOS circuits

Temperature dependent propagation delay characteristics of CMOS circuits will experience a complete reversal in the near future. Contrary to the older technology generations, the speed of standard zero-body-biased circuits in a 32 nm CMOS technology is enhanced when the temperature is increased at the nominal supply voltage. The enhancement of circuit speed provides new opportunities to lower the energy consumed by active circuits at elevated temperatures. Temperature-adaptive supply and threshold voltage tuning techniques are proposed in this paper to reduce the high temperature active mode energy consumption without degrading the circuit speed. Results indicate that the energy consumption can be lowered by up to 21% by dynamically scaling the supply voltage at elevated temperatures. An alternative technique based on temperature-adaptive reverse body-bias exponentially reduces the leakage currents as well as the parasitic junction capacitances of the MOSFETs. The temperature-adaptive threshold voltage tuning through reverse body-bias yields an active mode energy reduction by up to 29.8% as compared to the standard zero body-biased circuits at high temperatures.

Supply and Threshold Voltage Optimization for Temperature Variation Insensitive Circuit Performance: A Comparison

In this paper, the supply and threshold voltage optimization techniques to achieve temperature variation insensitive circuit performance are compared. The speed and energy tradeoffs with the two optimization techniques are presented.

Temperature-adaptive voltage tuning for enhanced energy efficiency in ultra-low-voltage circuits

Circuits optimized for minimum energy consumption operate typically in the subthreshold regime with ultra-low power-supply voltages. Speed of a subthreshold logic circuit is enhanced with an increase in the die temperature. The excessive timing slack observed in the clock period of subthreshold logic circuits at elevated temperatures provides opportunities to lower the active-mode energy consumption. A temperature-adaptive dynamic-supply voltage-tuning technique is proposed in this paper to reduce the high-temperature energy consumption without degrading the clock frequency in ultra-low-voltage subthreshold logic circuits. Results indicate that the energy consumption can be lowered by up to 40% by dynamically scaling the supply voltage at elevated temperatures. An alternative technique based on temperature-adaptive reverse body bias to exponentially reduce the subthreshold leakage currents at elevated temperatures is also investigated. The active-mode energy consumption with two temperature-adaptive voltage-tuning techniques is compared. The impact of the process parameter and supply voltage variations on the proposed temperature-adaptive voltage scaling techniques is evaluated.

TECHNIQUE FOR ACCURATE POWER AND ENERGY MEASUREMENT WITH THE COMPUTER-AIDED DESIGN TOOLS

Computer-aided design (CAD) tools are frequently employed to verify the design objectives before the fabrication of an integrated circuit. An important circuit parameter that requires accurate characterization is the power consumption due to the strict constraints on the acceptable power envelope of integrated systems. Circuit simulators typically provide built-in functions to measure the power consumption. However, the accuracy of the measured power is mostly overlooked since the approximations and the methodologies used by the existing built-in power estimation tools are not well documented. The research community tends to assume that the built-in functions provide accurate power figures. This blind-trust in the CAD tools, however, may lead to gross errors in power estimation. A generic methodology to accurately measure the power and energy consumption with the circuit simulators is described in this paper. An equation to calculate the device power consumption based on the different current conduction paths in a MOSFET is presented. An expression for the total power consumption of a complex circuit is derived by explicitly considering the different circuit terminals including the inputs, the outputs, and the body-contacts. Results indicate that the power measurements with the built-in functions of widely used commercial circuit simulators can introduce significant errors in a 65 nm CMOS technology. For deeply scaled nano-CMOS circuits, a conscious power and energy measurement with the proposed explicit methodology is recommended for an accurate pre-fabrication circuit characterization.