Rashmi Sachan

A 40nm 650Mhz 0.5fJ/Bit/Search TCAM Compiler Using Complementary Bit-cell Architecture

Ternary content addressable memory (TCAM) is used for high-speed table lookups. The dynamic power consumption of TCAMs is one of the main challenges for keeping up with high performance requirements. System level reliability is impacted by devices that produces large peak current demands on the power grid. This paper presents a TCAM compiler based on a static complementary TCAM bitcell for reduced dynamic power and reduced decoupling capacitance(dcap) requirement. The two stage architecture comprise of static TCAM cells with a match forward feature and then a static AND-tree structure. This TCAM compiler configurations have been implemented on 40nm CMOS technology testchip and experimental results demonstrate the performance upto 650Mhz and 0.5fJ/bit/search energy for a 512wordsx256bit macro.