Raul Camposano

Path-based scheduling for synthesis

A novel path-based scheduling algorithm is presented. It yields solutions with the minimum number of control steps, taking into account arbitrary constraints that limit the amount of operations in each control step. The result is a finite state machine that implements the control. Although the complexity of the algorithm is proportional to the number of paths in the control-flow graph, it is shown to be practical for large examples with thousands of nodes. >

High-Level VLSI Synthesis

1. Essential Issues and Possible Solutions in High-Level Synthesis.- 2. Architectural Synthesis for Medium and High Throughput Signal Processing with the new CATHEDRAL environment.- 3. PYSIN - High-Level Synthesis of Application Specific Pipelined Hardware.- 4. The IBM High-Level Synthesis System.- 5. MICON: Automated Design of Computer Systems.- 6. Cyber: High Level Synthesis System from Software into ASIC.- 7. Specification and Synthesis of Interface Logic.- 8. Synthesis of ASICs with Hercules and Hebe.- 9. Synthesis from Pure Behavioral Descriptions.- 10. Architectural Optimization Methods for Control-Dominated Machines.- 11. Global Scheduling and Allocation Algorithms in the HAL System.- 12. High-Level Synthesis in the THEDA System.- 13. Industrial Uses of the System Architects Workbench.- 14. Unified System Construction (USC).- 15. Scheduling and Assignment in High Level Synthesis.

Synthesizing circuits from behavioural descriptions

The authors discuss in detail the synthesis of structures from behavioural domain descriptions. The overall synthesis approach is explained, the techniques and methods used to solve the main problems are discussed, implementation results are given, and experiences with various examples are described. The principal topics that are addressed are design description in the behavioural domain using a formal language, internal representation of the behaviour, synthesis based on data-flow analysis, optimizations and generation of a hardware structure. These techniques were implemented in the Karlsruhe DSL synthesis system. >

Embedded system design

In the past decade the main engine of electronic design automation has been the widespread application of ASICs (Application Specific Integrated Circuits). Present technology supports complete systems on a chip, most often used as so-called embedded systems in an increasing number of applications. Embedded systems pose new design challenges which we believe will be the driving forces of design automation in the years to come. These include the design of electronic systems hardware, embedded software and hardware / software codesign. This paper explores the novel technical challenges in embedded system design and presents experiences and results of the work in this area using the CASTLE system. CASTLE supports the design of complex embedded systems and the design of the required tools. It provides a central design representation, Verilog, VHDL and C/C++ frontends, Hardware generation in VHDL and BLIF, a retargetable compiler backend and several analysis and visualization tools. Two design examples, video compression and a diesel injection control, illustrate the presented concepts.

From behavior to structure: high-level synthesis

This paper shows how high-level synthesis bridges the gap between behavioral specifications and hardware structure by automatically generating a circuit description from a netlist. The resulting description can be used for other design automation tools, such as logic synthesis and layout. As opposed to logic synthesis, which optimizes only combinational logic, high-level synthesis deals with memory elements, the interconnection structures, (such as buses and multiplexers), and the sequential aspects of a design. The steps in the process of synthesizing synchronous digital hardware are explained. They consist of compilation, high-level transformations, scheduling, and allocation. Design representation is discussed, and problems remaining to be solved are indicated.<<ETX>>

An industrial view of electronic design automation

The automation of the design of electronic systems and circuits [electronic design automation (EDA)] has a history of strong innovation. The EDA business has profoundly influenced the integrated circuit (IC) business and vice-versa. This paper reviews the technologies, algorithms, and methodologies that have been used in EDA tools and the business impact of these technologies. In particular, we focus on four areas that have been key in defining the design methodologies over time: physical design, simulation/verification, synthesis, and test. We then look briefly into the future. Design will evolve toward more software programmability or some other kind of field configurability like field programmable gate arrays (FPGAs). We discuss the kinds of tool sets needed to support design in this environment.

VHDL as input for high-level synthesis

High-level synthesis is defined, and the feasibility of high-level synthesis from a behavioral, sequential description in VHDL (VHSIC hardware description language) is examined. It is seen that in some cases the semantics and descriptive power of the language create difficulties for high-level synthesis, and in other cases the high-level synthesis framework used imposes limitations. Restrictions in the form of rules are suggested for overcoming these difficulties. It is shown that although VHDL semantics were initially defined in terms of simulation, they do not pose any fundamental problems for high-level synthesis.<<ETX>>

Synthesis using path-based scheduling: algorithms and exercises

Path-based scheduling algorithms consider all possible sequences of operations (called paths) in a control-flow graph. Unlike most scheduling techniques used in high-level synthesis, they stress optimization across conditional branches. This paper presents several path-based algorithms. An exact algorithm finds the minimum number of control steps required for each possible path being executed. Heuristic solutions were also implemented. Extensive application of these algorithms to the benchmarks of the High-Level Synthesis Workshop showed the practical feasibility of such methods.

Behavioral synthesis

Since the 1988 tutorial on behavioral (high-level) synthesis which appeared in the DAC proceedings (and later in the proceedings of the IEEE) much has happened in the field. Behavioral synthesis is now considered mainstream EDA as evidenced by the number of articles at conferences, journals and books. May be even more significant, several products are being offered commercially, and the number of designers using behavioral synthesis is probably in the hundreds. The initial promise of behavioral synthesis, to dramatically increase productivity by elevating the level of design, has been fulfilled. The increase in productivity of behavioral design versus RTL design is typically quoted at 5 times. What came as a surprise to most researchers in the field, is that this is achieved without impacting the quality of results (area, timing)! If anything, behavioral designs are slightly smaller and faster that their RTL counterparts, mainly because much more architectural exploration can be afforded at the behavioral level, thus providing a better starting point for synthesis.

Behavior-preserving transformations for high-level synthesis

This paper addresses the synthesis of a circuit structure from a sequential behavioral specification. The problem is formally stated as a sequence of behavior-preserving transformations of a data- and control-flow graph. Behavior equivalence is defined strongly, so that it implies equal output sequences for equal input sequences and equal initial state. The transformations introduce the minimum number of control steps. The resulting structure includes both control and data-path. The combinational logic in this structure is passed to logic synthesis for further optimization. Several examples illustrate these techniques, giving results down to the logic level.