Raul Onet

Compact Variable Gain Amplifier for a Multistandard WLAN/WiMAX/LTE Receiver

This paper presents a novel single-stage VGA architecture that employs two Gm cells, a voltage-controlled current attenuator, resistors and capacitors. The gain can be changed in three large steps by using digital controls, and continuously within these steps. The VGA bandwidth and output-related IP3 and 1dBCP are independent of the gain setting; the bandwidth can be programmed through a digitally-controlled capacitor array placed at its output. The proposed architecture was employed to realize the VGA for a WLAN/WiMAX/LTE radio receiver. Die area and power consumption were reduced by implementing the two Gm cells with one instantiation of a high-linearity Gm-core and scaled outputs; also, the current attenuator was implemented with a simple differential current steering circuit; finally, the load resistors were also used to sense the output common-mode level. The VGA was fabricated in 0.15 um standard CMOS process. Measurement results show the gain varying between -5 dB to 30 dB and the max bandwidth surpasses 60 MHz; 11.14 nV/√{Hz} input referred noise; O1dBCP of 8.6 dBm while taking 4.2 mA from a 1.8 V supply; it settles within 20 ns after a min-max step-change of the gain; it occupies 0.05 mm2.

Matlab modeling and analysis of the signal path in Zero-IF DVB-T/H radio receivers

This paper presents a Matlab model for the signal path within a DVB-T receiver, along with a new method for analyzing the effects various block nonidealities have on the receiver, when considering unwanted signals such as the adjacent channels and out-of-band blockers. The models for amplifier-type blocks cover not only the basic parameters - gain, bandwidth - but also the noise - though the noise factor - and the nonlinearity - through the compression and intercept points. Additional features are provided for blocks with more specific functions: gain imbalance and quadrature error are added in for the mixer model, frequency characteristics for channel filters models, quantization error for the analog-to-digital converter. The model also comprises an OFDM signal generator and the DSP block. The proposed analysis method is based on a direct, sample-by-sample, comparison between a reference signal - obtained by using a reference version of the receiver, for which some aspects are idealized - and the “real” signal, obtained by using the complete receiver model and considering all signals, wanted and unwanted.

Comparative Analysis of Simulation-Based Methods for Deriving the Phase- and Gain-Margins of Feedback Circuits With Op-Amps

Ten methods for finding through simulations the small-signal phase and gain margins of feedback circuits based on op-amps are described and analyzed in this mostly tutorial paper. The testbenches employed by these methods are presented and the corresponding analytical expressions of the return ratio are derived and compared against their “ideal” counterpart, obtained with standard circuit analysis; the requirement that the return ratio should not depend on the point it was measured at is also verified. These analyses are performed on a fairly general case: a generic reciprocal two-port network that closes a feedback loop around an op-amp acting as the forward amplifier. The four main types of op-amps were considered. The limitations of some of the tested methods are then highlighted by simulations. Besides the detailed analysis of previously reported methods, the paper proposes a novel method for deriving the return ratio of feedback circuits, that employs only current stimuli; it is demonstrated analytically that this method can be used for bilateral circuits, not only for op-amp-based (unilateral) ones. Also, a recent method for deriving directly the phase margin of a circuit is extended to estimating the gain margin, too. Conclusions on the accuracy and suitability of the analyzed methods for practical circuit cases are drawn. These results are then extended to other circuit topologies.

A new OTA-C universal biquad resonates out the main parasitic capacitance

This paper proposes a core structure that provides, with minimum of adjustments, a wide range of second-order transfer functions, from the usual low-pass and band-pass to transfer functions with imaginary and complex zeroes. This universal biquad is implemented with transconductors and grounded capacitors. The performances of similar structures reported in the literature are significantly degraded by the parasitic capacitances present at their internal modes, especially those nodes without a placed capacitance. The biquad proposed here provides a way of resonating out the main parasitic capacitance, pushing most of its effects out of the band of interest. A design example demonstrates that this structure is suitable for the implementation of integrated filters operating in the tens of MHz frequency range.

A voltage-controlled amplifier based on Gm cells for multistandard OFDM integrated receivers

This paper presents a variable-gain amplifier (VGA) based on transconductors (Gm cells); it consists of two instantiations of the same Gm core and three scaled output stages. The core is optimized for high linearity that is not affected by the gain setting as the gain variation is achieved through a differential current steering scheme. The proposed VGA is well suited for multistandard radio receivers: its bandwidth and linearity are largely independent of the gain setting and both the gain range and the bandwidth can be programmed through digital controls. The structure is fully differential, with the output common-mode voltage controlled by a novel scheme, that does not require the placement of additional circuitry in the differential signal path. The VGA was designed in a standard 0.18um CMOS technology; simulation results show that it can cover the gain range of −6dB to +24dB while handling signals with amplitudes up to 1Vpkpkdiff without significant distortions. The bandwidth remains above 40MHz while driving up to 1pF and can be controlled through the programmable capacitance placed at the VGA output. The VGA power consumption is 7mW for gains up to 18dB and 12mW above than, from a 1.8V supply.

Optimization of the channel filter in OFDM radio receivers by using genetic algorithms

This paper proposes a novel method for deriving optimized transfer functions for channel filters in OFDM receivers with Zero Intermediate Frequency architectures. A genetic algorithm is employed, based on only three selection criteria that independently control the pass band and the stop band of the filter. Another special feature of this method is that the disruptive effect of the signals from the adjacent bands is analyzed in detail by using a purpose-built OFDM signal generator. This way the mean attenuation in the adjacent band can be maximized effectively. A Matlab implementation of the proposed method is presented, along with a design example.

Enabling area efficient RF ICs through monolithic 3D integration

The Monolithic 3D (M3D) integration technology has emerged as a promising alternative to dimensional scaling thanks to the unprecedented integration density capabilities and the low interconnect parasitics that it offers. In order to support technological investigations and enable future M3D circuits, M3D design methodologies, flows and tools are essential. Prospective M3D digital applications have attracted a lot of scientific interest. This paper identifies the potential of M3D RF/analog circuits and presents the first attempt to demonstrate such circuits. Towards this, a M3D custom design platform, which is fully compatible with commercial design tools, is proposed and validated. The design platform includes process characteristics, device models, LVS and DRC rules and a parasitic extraction flow. The envisioned M3D structure is built on a commercial CMOS process that serves as the bottom tier, whereas a SOI process is used as top tier. To validate the proposed design flow and to investigate the potential of M3D RF/analog circuits, a RF front-end design for Zig-Bee WPAN applications is used as case-study. The M3D RF front-end circuit achieves 35.5 % area reduction, while showing similar performance with the original 2D circuit.

Comparative analysis of four second-order OA-RC polyphase filters for an ISM Low-IF receiver

This paper presents the comparative analysis of four implementation of a polyphase filter with the IF frequency of 1MHz and the passband width of 700 kHz. All versions employ the OA-RC technique but have different topologies: the classical structure based on lossy integrators, then two structures derived from the well-known Tow-Thomas and Sallen-Key real biquads and a novel topology, based on the Rauch structure. First, the requirements for the active cell - the OA - are derived by analysing the effects the OA finite gain-bandwidth product and (possible large) output resistance has on the filter performance for each topology; then an OA that meets the requirements is designed in a standard 0.18um CMOS process, optimized for low power consumption. The extensive set of simulation results presented here allows a detailed comparison between the four designs, targeting same specifications.

Analysing the stability of series-shunt circuits based on voltage- and current- feedback OpAmps through SPICE AC simulations

Two methods for determining the loop gain of OpAmp-based circuits with series-shunt feedback through simulations are analyzed and compared: the standard method — that involves breaking the feedback loop by inserting an independent voltage source with DC=0 and AC=1 — and a more precise method, based on the Rosenstark theorem. Only the cases for the traditional (voltage-feedback) and the current-feedback OpAmps are discussed in the paper but the conclusions can be extended to other types of amplifiers.

Comparison between three structures of high speed low-voltage and low-dropout linear regulators

Biasing digital CMOS circuits with rapidly changing supply current requires fast load regulation. Integrating the regulator with no external components on the same chip with the load circuit is attractive for applications with stringent volume and weight requirements. The purpose of this paper is the analysis, design and comparison of three structures of high-speed linear regulators implemented in MOS technologies: a fast regulator recently presented in the literature, that combines a low-bandwidth control loop with fast open-loop buffers, and two structures proposed by the authors - one derived from the standard linear regulator but with improved frequency compensation and the other obtained by combining the first two approaches. The discussion is focused on the response time of these regulators to fast and large variations of the load current, specific to the supplying of digital circuits.