Ravi Kumar Satzoda

A Low Error and High Performance Multiplexer-Based Truncated Multiplier

This paper proposes a novel adaptive pseudo-carry compensation truncation (PCT) scheme, which is derived for the multiplexer based array multiplier. The proposed method yields low average error among existing truncation methods. The new PCT based truncated array multiplier outperforms other existing truncated array multipliers by as much as 25% in terms of silicon area and delay, and consumes about 40% less dynamic power than the full-width multiplier for 32-bit operation. The proposed truncation scheme is applied to an image compression algorithm. Due to its low truncation error, the mean square errors (MSE) of various reconstructed images are found to be comparable to those obtained with full-precision multiplication.

Hierarchical Additive Hough Transform for Lane Detection

Detection of lanes is an important problem in the upcoming field of vehicle safety and navigation, for which linear Hough transform (HT) is widely used. In order to meet real-time requirements, various attempts to accelerate the HT have been proposed in the past, including hierarchical HT. Existing hierarchical approaches involve the overhead of recomputing HT values at every level in the hierarchy. In this letter, we propose a novel, computationally efficient hierarchical HT by extending and applying the additive property of HT to multiple levels of hierarchies. This proposed approach, called hierarchical additive Hough transform (HAHT) is shown to lead to significant computational savings of up to 98-99% in the Hough voting process. The HAHT has been validated on a wide range of straight lane images and it is shown to successfully detect lanes.

Exploiting Inherent Parallelisms for Accelerating Linear Hough Transform

Accelerating Hough transform in hardware has been of interest due its popularity in real-time capable image processing applications. In most existing linear Hough transform architectures, an m times medge map is serially read for processing, resulting in a total computation time of at least m2 cycles. In this paper, we propose a novel parallel Hough transform computation method called the Additive Hough transform (AHT), wherein the image is divided using a k times k grid to reduce the total computation time by a factor of k2. We have also proposed an efficient implementation of the AHT consisting of a look-up table (LUT) and two-operand adder arrays for every angle. Techniques to condense the LUT size have also been proposed to further reduce area utilization by as much as 50%. Our investigations based on employing an 8 times 8 grid shows a 1000 times speedup compared to existing architectures for a range of image sizes. Area-time trade-off analysis has been presented to demonstrate that the area-time product of the proposed AHT-based implementation is at least 43% lower than other implementations reported in the literature. We have also included and characterized a hierarchical addition step in order to generate a global accumulation space equivalent to that of the conventional HT. It is shown that the proposed implementation with the hierarchical addition step remains superior to other methods in terms of both performance and area-time product metrics. Finally, we show that the proposed solution is equally efficient when applied on rectangular images.

Gradient angle histograms for efficient linear hough transform

Non-collinear edge pixels are equivalent to noise for the linear Hough transform (LHT). Existing methods that reduce the number of points for Hough voting are based on random and/or probabilistic selection. Such methods select both collinear and noisy pixels, thereby incurring unwanted computational costs. In this paper, we propose a novel gradient angle histogram based technique to generate modified straight line edge map (SLEM), which largely retains the straight line edges and eliminates noisy edge pixels. A block-based SLEM generation is proposed to increase the robustness of straight line extraction and validated on test images. Further, effect of varying block sizes on accuracy of straight line detection is studied and appropriate block settings are derived. The proposed gradient angle histogram based method reduces the number of edge pixels by as much as 85%.

Unified Cordic Based Processor for Image Processing

The CORDIC algorithm, owing to its hardware efficiency, has been widely employed for computing complex mathematical operations. In this paper, a unified CORDIC-based processor for image processing is presented. For this, a wide range of popular algorithms like image enhancement in the spatial domain, frequency transforms, image rotation, edge detection etc. are chosen and their implementation using CORDIC is investigated. An integrated architecture that exploits the different operating modes of CORDIC is proposed employing an array of CORDIC-based processing elements. A qualitative analysis of the processor in terms of computation cycles and area complexity to process an entire image of size M × N is also presented.

Identifying lane types: A modular approach

Lane detection is a problem that has been extensively studied by the research community in the past two decades. However limited literature can be found on techniques to distinguish the various types of lane markings - such as solid, dashed, single, double, zigzag etc. In this paper, we present a modular approach to detect and distinguish a wide range of lane markings. The fundamental processing module for detecting basic lane markings (BLM) is first proposed, after which we show how this can be deployed for distinguishing the various lane marking types. The underlying principle is that any lane marking can be broken down into one or more BLMs. A modular architecture is presented to detect and distinguish the various lane markings using the proposed modules. The techniques are evaluated on the road marking dataset in [8] and is shown to yield a high detection accuracy.

Vision-based vehicle queue detection at traffic junctions

Real-time traffic queue detection can directly aid in dynamic traffic light control at road junctions. In this paper, we propose an efficient technique to detect vehicle queue lengths at traffic junctions based on progressive block based image processing. We also propose a two-step approach for vehicle detection that relies on edges and dark features in the image. It is shown that this vehicle detection approach is robust to heavy and light shadows. Further, the threshold adapts itself dynamically to handle varying light conditions. Evaluation of the proposed method using over 45 real video sequences shows nearly 100% accuracy in vehicle detection and queue length estimation.

A novel multiplexer based truncated array multiplier

The design of high-speed, area-efficient and low power multiplier is essential for the VLSI implementation of DSP systems. In many applications, like digital filtering, the inputs are contaminated by noise and precise outputs are often not required. It has been shown that the area and power of multiplier can be significantly reduced by truncation techniques at the expense of truncation errors. This paper presents a novel multiplexer based truncated array multiplier, which has leveraged and improved upon three existing truncation algorithms. An exhaustive error analysis was also performed to evaluate the truncation errors of the new truncated multiplier. The proposed truncated multiplier was compared to one implemented with the standard truncation schemes in latency, silicon area and power dissipation. Simulation results have attested the accuracy and VLSI performance ascendancy of the proposed truncated multiplier.

Block-Based Search Space Reduction Technique for Face Detection Using Shoulder and Head Curves

Conventional face detection techniques usually employ sliding window based approaches involving series of classifiers to accurately determine the position of the face in an input image resulting in high computational redundancy. Pre-processing techniques are being investigated to reduce the search space for face detection. In this paper, we propose a systematic approach to reduce the search space for face detection using head and shoulder curves. The proposed method includes Gradient Angle Histograms (GAH) that are applied in a block-based manner to detect these curves, which are further associated to determine the search space for face detection. A performance evaluation of the proposed method on the datasets (CASIA and Buffy) shows that an average search space reduction upto 80% is achieved with detection rates of over 90% for specific parameters of the dataset.

Performance evaluation of direct form FIR filter with merged arithmetic architecture

This paper demonstrates a novel design concept and optimization method towards the design of low power FIR filters for a fixed coefficient set. The prowess of merged arithmetic architecture is capitalized in the direct form filter structure to avoid the total number of accumulators and the lengths of the registers from being increased progressively with the filter taps. A delay profile driven adder is designed to further exploit the uneven signal arrival time at the final stage of the Carry Save Adder (CSA) tree. The performance of the proposed filter structure has been evaluated by comparing its prototype with two other optimized transposed direct form filter designs, implemented with the same process technology.