Raymond Peterkin

Hardware support of JPEG

Image formats specified by the joint photographic expert group (JPEG) are preferred for images with high colour content. Along with graphic interchange format (GIF) images, JPEG is the most commonly used image format on the Internet and JPEG is the de facto still image format for digital cameras. All major digital camera manufacturers use JPEG as its exclusive or primary still image format. Most JPEG processing occurs in software programs like Microsoft Paint and Adobe Photoshop. Relatively few hardware solutions exist for processing JPEG images. This paper presents a comprehensive literature survey of hardware solutions for JPEG images. Wherever possible, different JPEG formats and accompanying hardware are presented and compared to illustrate various advantages/disadvantages. The performance of hardware and software for JPEG is compared and an overview of commercial hardware for JPEG is also provided

A High-Performance Architecture of an XML Processor for SIP-Based Presence

With the widespread popularity of XML, many communication and multimedia standards are being developed based completely or partially on XML. The Session Initiation Protocol is a signaling mechanism - frequently used for Multimedia applications - that comprises XML-based “presence” information particularly useful in Instance Messaging.The process of XML parsing and serialization is needed repeatedly during the exchange of presence notification messages in such systems. However, XML processing is known to be time-consuming. In instant messaging systems, especially when mobile users are involved, presence update notification is frequent and has to be fast to save mobility time and battery resources. In this paper, we present a high-performance architecture of an XML processor customized for efficiently processing presence information. Our FPGA implementation results show that at least two bytes of XML data can be parsed on average in each clock cycle, which leads eventually to a high-throughput processor.

A Hardware/Software Co-Design for RSVP-TE MPLS

This paper presents a hardware/software co-design for multi protocol label switching (MPLS) using RSVP-TE as a signaling protocol. MPLS is the protocol framework on which the attention of network service provider is focused as it provides privacy and unbreakable security to users. It is meant to primarily prioritize Internet traffic and improve bandwidth utilization. As such it provides the possibility of associating quality of service per flow. Furthermore it increases the performance of Internet applications and overall efficiency. MPLS solutions are meant to be used with layer 2 and or layer 3 protocols. So far MPLS protocols are implemented by equipment providers in the equipment software package. However, software based solutions decrease overall performance of the network. This paper introduces a new FPGA based hardware architecture through which the overall MPLS performance is enhanced by executing core tasks in hardware while allowing other tasks to be executed in the associated FPGA processor to guard against performance degradation. The hardware component is emphasized with descriptions of its architecture and performance

Embedded MPLS architecture

This paper presents a hardware architecture for multiprotocol label switching (MPLS). MPLS is a protocol used primarily to prioritize Internet traffic and improve bandwidth utilization. Furthermore it increases the performance of Internet applications and overall efficiency. However, most existing MPLS solutions are entirely software based. MPLS performance can be enhanced by executing core tasks (i.e. label stack modification) in hardware while allowing other tasks to be executed in software to guard against performance degradation. This paper proposes a hardware/software design of MPLS on an FPGA for increased performance and efficiency. Greatest emphasis is placed on the hardware components.

Hardware implementation of session initiation protocol servers and clients

This paper presents a reconfigurable architecture for the session initiation protocol (SIP). SIP is a protocol used primarily to establish point-to-point sessions between users for multimedia communication. Furthermore it increases the performance of Internet applications and overall efficiency. However, most existing SIP solutions are entirely software based. SIP performance can be enhanced by executing core tasks in hardware while allowing other tasks to be executed in software to guard against performance degradation. This paper proposes an architecture of SIP implementable on reconfigurable platforms (FPGAs) for increased performance and efficiency.

A reconfigurable architecture for IP Multimedia Subsystem session setup

The architecture of IP Multimedia Subsystem (IMS) enables converged voice, video, and data services and contains mechanisms related to session and connection control. Numerous protocols are used to perform IMS operations however the Session Initiation Protocol (SIP) plays a central role in the functionality of IMS. With increased demand for multimedia communications functionality, a software implementation of IMS limits performance and increases power consumption when controlling applications through devices like gateways, proxies and application servers. Therefore a strong desire exists to implement SIP using low power consumption hardware platforms very fast time responses. The large integration scale of the present chip technology allows for implementing all SIP mechanisms and interfaces in a single integrated chip or ASIC. In this paper, a reconfigurable hardware implementation of the session setup of IMS is described based on a hardware implementation of SIP.

Role Based Access Control for UDDI Inquiries

Web services are commonly used by organizations for B2B integration and enterprise application integration. UDDI registries are widely used as mechanisms for businesses to list and discover available services. Businesses may want to limit the information of their services to certain users and businesses. However, UDDI provides no mechanisms to limit data inquiries to a particular subset of requesters. This paper presents a role-based access control implementation of UDDI so businesses may safely publish data and limit the organizations who may perform inquiries against their information.

An Architecture for Heterogeneous Data Dissemination Using IMS

This paper presents an architecture to define and disseminate heterogeneous data between multiple participants in real-time using the IP Multimedia Subsystem (IMS) with Field Programmable Gate Array (FPGA) development platforms. IMS is a communications framework permitting the exchange of data between communications devices across divergent networks. Mechanisms are defined in IMS for users to create subscriptions to receive data from multiple participants. Users are limited to the types of data that can be received through a subscription and no known mechanisms are available to control the rate at which data may be received. This paper presents an architecture to address these issues by permitting users to describe the means through which heterogeneous data can be transmitted. Modifications are introduced to the IMS subscription mechanism increasing the efficiency of data delivery through the Session Initiation Protocol (SIP). These changes are implemented into a FPGA platform so data may be exchanged through IMS while limiting performance bottlenecks as much as possible.

An Architecture for Mobile Sensor Network Control Using IMS and Reconfigurable Hardware

Mobile sensors networks are used in several domains to perform various tasks related to monitoring, recording, and affecting the conditions of an environment. Interacting with mobile sensor networks deployed in public networks requires an application capable of securely exchanging data in the network, generating mobile sensor network requests and processing mobile sensor network responses. Embedded communications devices are an ideal platform through which mobile sensor network applications could be implemented due to their portability and preexisting facilities to establish network connections. The IP Multimedia Subsystem (IMS) is a communications framework permitting the exchange of data from communications devices across divergent networks. No research has been performed combining embedded devices and mobile sensor networks using public network facilities like IMS. This paper proposes an architecture permitting end users to perform mobile sensor network operations using IMS and embedded communications devices. The architecture is based on a reconfigurable hardware implementation of SIP to exchange data through an IMS network to query mobile sensor data, publish data to valid subscribers and control nodes. SIP is used to manage the sessions in which data are accessed by arbitrary users registered with a sensor network service.

A hardware implementation of layer 2 MPLS

This paper presents a hardware architecture for layer 2 Multi Protocol Label Switching (MPLS). MPLS is a protocol framework used primarily to prioritize internet traffic and improve bandwidth utilization. Furthermore it increases the performance of internet applications and overall efficiency. However, most existing MPLS solutions are entirely software based which decreases performance. MPLS performance can be enhanced by executing core tasks in hardware while allowing other tasks to be executed in software to guard against performance degradation. This paper proposes a hardware design of MPLS on an FPGA for increased performance and efficiency.