Razak Hossain

A Fully Digital 65nm CMOS Transmitter for the 2.4-to-2.7GHz WiFi/WiMAX Bands using 5.4GHz ΔΣ RF DACs

This paper describes a fully digital CMOS transmitter that meets the IEEE 802.11 b/g and 802.16e standards in the 2.4-to-2.7 GHz band, while taking into account the coexistence requirements when used in 2G/3G mobile handsets. The baseband signal is upsampled first to a sampling rate FM around 160MHz, using FIR interpolators. I/Q and DC precompensation is then applied, to eliminate the image and LO components at the RF output. A first fine digital gain stage controls the signal level in a 0 to -12 dB range. The baseband signal is then upsampled to Fc/4, where Fc is the carrier frequency in the 2.4 to 2.7 GHz range. As the ratio between Fc/4 and FM is not necessarily integer, a fractional-N interpolator has to be used. The interpolating ratio has 17 bits of resolution, which allows carrier frequencies on a 25 kHz raster, to satisfy all possible WiFi and WiMAX channel allocations.

A Scalable 2.4-to-2.7GHz Wi-Fi/WiMAX Discrete-Time Receiver in 65nm CMOS

This paper describes a fully integrated scalable discrete-time receiver based on a merged SC mixer, filter and SAR ADC meeting the requirements of IEEE 802.16e and 802.11b/g/n standards. Recent work has shown the use of SC-filtering techniques in radio receivers, where sampling is done early in the RX path. Such discrete-time architectures require an early anti-aliasing (AA) filter prior to sampling. Multiple AA and channel filters with decimation stages have been used to strongly attenuate alias and adjacent channels and to allow sampling of the signal at a reasonable rate at the ADC stage.IF amplifiers are necessary to drive ADC input stage. The direct-conversion receiver architecture proposed here is based on a fully-passive CMOS approach. It is composed of one transconductance LNA and a resistive attenuator.

The iCore 520-MHz synthesisable CPU core

A new implementation of the ST20-C2 CPU architecture involves an eight-stage pipeline with hardware support to execute up to three instructions per cycle. The design operates up to 520 MHz at 1.8V, among the highest reported speeds for a synthesized CPU core.

The iCOREtm 520 MHz synthesizable CPU core

This paper describes a new implementation of the ST20-C2 CPU architecture. The design involves an eight-stage pipeline with hardware support to execute up to three instructions in a cycle. Branch prediction is based on a 2-bit predictor scheme with a 1024-entry Branch History Table and a 64 entry Branch Target Buffer and a 4-entry Return Stack. The implementation of all blocks in the processor was based on synthesized logic generation and automatic place and route. The full design of the CPU from microarchitectural investigations to layout required approximately 8-man years. The CPU core, without the caches, has an area of approximately 1.5 mm2 in a 6-metal 0.18m CMOS process. The design operates up to 520 MHz at 1.8V, among the highest reported speeds for a synthesized CPU core [1].

The iCORE/spl trade/ 520 MHz synthesizable CPU core

This paper describes a new implementation of the ST20-C2 CPU architecture. The design involves an eight-stage pipeline with hardware support to execute up to three instructions in a cycle. Branch prediction is based on a 2-bit predictor scheme with a 1024-entry Branch History Table, a 64-entry Branch Target Buffer and a 4-entry Return Stack. The implementation of all blocks in the processor was based on synthesized logic generation and automatic place and route. The full design of the CPU from microarchitectural investigations to layout required approximately 8-man years. The CPU core, without the caches, has an area of approximately 1.5 mm/sup 2/ in a 6-metal 0.18 /spl mu/m CMOS process. The design operates up to 520 MHz at 1.8 V, among the highest reported speeds for a synthesized CPU core.