Reda R. Razouk

Interface States and Electron Spin Resonance Centers in Thermally Oxidized (111) and (100) Silicon Wafers

Interface states and electron spin resonance centers have been observed and compared in thermally oxidized (111) and (100) silicon wafers subjected to various processing treatments. The ESR Pb signal, previously assigned to interface ⋅Si≡Si3 defects on (111) wafers, was found to have two components on (100): an ⋅Si≡Si3 center oriented in accord with (100) face structure, and an unidentified center consistent with ⋅Si≡Si2O. The quantitative proportionality of Pb spin concentration to midgap interface trap density Dit is maintained on (100), and both are lower by a factor of about 3 compared to (111). This correlation persists over the range of oxidation temperatures 800–1200°C, for both n‐ and p‐doped silicon, cooled by fast pull in oxygen, and cooled or annealed in nitrogen or argon. The correlation is independent of doping level. In samples with different oxide thickness, neither Pb nor Dit varied significantly over the range 100–2000 A, but Pb was smaller at 50 A. In general, ESR is judged to offer prom...

ESR centers, interface states, and oxide fixed charge in thermally oxidized silicon wafers

The ESR Pb center has been observed in thermally oxidized single‐crystal silicon wafers, and compared with oxide fixed charge Qss and oxidation‐induced interface states Nst. The Pb center is found to be located near the interface on (111) wafers. Its g anisotropy is very similar to that of known bulk silicon defects having SiIII bonded to three other Si atoms; the Pb unpaired electron orbital, however, is exclusively oriented normal to the (111) surface. The Pb center cannot be identified with any other known defect in Si or SiO2; in particular, it is totally unlike the common E′ center of SiO2. In contrast to Qss, both Pb and Nst were found to be greatly reduced by steam oxidation and hydrogen annealing. Both Pb and Nst may be regenerated by subsequent N2 anneals at 500u2009°C. In a graded series of samples, Pb and Nst are found to be proportional and nearly equal in concentration. This possible confirmation of SiIII at the interface, and correlation with Nst, support the theoretical indication of an SiIII b...

Dependence of Interface State Density on Silicon Thermal Oxidation Process Variables

The structural or intrinsic type of interface state charge, related to thermal oxidation and annealing processes, has been characterized with respect to silicon thermal oxidation variables using quasistatic C‐V techniques. Those variables include oxidation ambient (, , ), annealing/cooling ambient (, , Ar), oxidation temperature (800°–1200°C), silicon type (p‐ and n‐type), and orientation [(111) and (100)]. Oxides (1200–2200A thick) annealed and cooled from any oxidation temperature in nitrogen or argon exhibit large interface state densities as oxidized. However after a low temperature hydrogen anneal these densities are lower than those of comparable oxygen‐cooled oxides. Interface state densities of oxides cooled in oxygen vary inversely with oxidation temperature before and after postmetallization anneals. This temperature relationship is very similar to that reported previously for oxide fixed charge and helps to substantiate a model based on a common origin of interface states and oxide fixed charge.

Kinetics of High Pressure Oxidation of Silicon in Pyrogenic Steam

The kinetics of high pressure oxidation of silicon in pyrogenic steam were investigated for ambient pressures of 5–20 atm and for oxidation temperatures of 800°–1000°C. A linear‐parabolic model was used in the analysis of the data. Both rate constants of the analytic model were found to be linearly proportional to pressure for the entire range of temperature and pressure. Fixed oxide charge and interface state densities for oxides grown at high pressure were found to be slightly higher at lower temperatures, particularly below 900°C, than for oxides grown at 1 atm. Electron trapping by avalanche injection in oxides grown on (111) Si at 5 atm in pyrogenic steam (800°C) yielded effective trap densities and capture cross sections similar to those obtained at 1 atm.

An advanced single-level polysilicon submicrometer BiCMOS technology

An advanced VLSI (very large scale integration) technology providing high-performance n-p-n bipolar (f/sub T/=9 GHz) and submicrometer gate-length MOS (metal-oxide-semiconductor) transistors is described. This technology is intended for high-speed logic circuits operating at 5 V, where a high level of circuit integration and low power consumption is required. Features include vertical n-p-n transistors with walled, self-aligned polysilicon emitters and lightly doped extrinsic base (LDEB) extensions MOS transistors feature complementary-doped polysilicon gates and LDD (lightly doped drain) structures for both NMOS and PMOS. Optional buried contacts between the polysilicon layer and all junctions in the silicon substrate are provided. Polysilicon emitters, MOS gates, base/collector, and source/drain regions are silicided. In addition, a fully planarized metal interconnect scheme incorporating nonselective CVD (chemical-vapor-deposited) tungsten and vertical-walled contacts and vias is utilized. >

Oxidation of tantalum disilicide/polycrystalline silicon structures in dry O2

The oxidation kinetics of tantalum disilicide/polycrystalline silicon composite structures in a dry O2 ambient have been investigated. The formation of silicon dioxide films on the tantalum disilicide was observed for all temperatures evaluated in the range of 800–1000u2009°C. The oxidation is postulated to occur as a result of the diffusion of silicon from the underlying polycrystalline silicon film through the TaSi2 film. The linear oxidation rate constant is substantially higher than that for the oxidation of single crystal silicon. The oxidation rate was found to be primarily controlled by the diffusion of the oxidant species through the forming oxide resulting in parabolic growth. The parabolic rate constant determined is similar to that obtained in the oxidation of single‐crystal silicon with an activation energy of approximately 28 kcal/mol. This value has been previously related to the diffusivity of oxygen through fused silica.

A four‐phase complex refractive index model of ion‐implantation damage: Optical constants of phosphorus implants in silicon

A four‐phase complex refractive index‐model approximation coupled with multiple‐angle‐of‐incidence ellipsometric measurements is utilized in an analysis of ion‐implantation damage in silicon. The four phases refer to the ambient, native oxide, implant layer, and substrate. The analysis is applied to phosphorus implants as functions of various ion‐dose ranging from 5×1012 to 1×1016 ions cm−2, and effective energies from 36 to 120 KeV, for both monomer (P+) and dimer (P+2) species. Implant depths are found to be related to the implant parameters and are found to be equal to RP +1.08 ΔRP where RP is the projected range and ΔRP is the projected standard deviation of the implanted ion. This relationship is invariant with respect to effective energy, ion dose, and species. Changes in refractive index, extinction coefficient, and reflectivity are readily detected at doses as low as ∼1013 ions cm−2. A decrease in extinction coefficient at high doses suggests that ion‐beam annealing is occurring. In general, chang...

Oxide charges induced in thermal silicon dioxide by scanning electron and laser beam annealing

Oxide charge generation resulting from the exposure of Si/SiO2 structures to scanning electron and laser beams during the anneal of ion implantation damage was investigated. Fixed oxide charge, interface trapped charge, and oxide trapped charge densities were measured by use of high‐frequency, quasistatic C‐V, and avalanche carrier injection techniques. The effective density of traps induced by the exposure of thin oxides to electron beam fluences of 0.39–3.10×10−2 C/cm2 at 5 kV was found to be an order of magnitude larger than in control wafers. This effect was primarily due to neutral trap formation. Although interface charges could be reduced to an acceptable level by a post‐irradiation anneal (400 to 500u2009°C) in forming gas, neutral traps could not be annealed satisfactorily. It was also found that scanned electron‐beam annealing from the backside of the wafer or laser annealing constitute viable alternatives with minimal effects on the densities of fixed oxide charges in the silicon dioxide layer.

Use of the polysilicon gate layer for local interconnect in a CMOS technology incorporating LDD structures

In conventional single-level polysilicon technologies, the polysilicon gate layer can be used as an interconnect layer through buried contacts between polysilicon and one type of junction (usually n/sup +/) in the underlying substrate. The formation and characteristics of buried contacts between n/sup +/ and p/sup +/ junctions and a single polysilicon gate layer are discussed. In addition, it is shown that the obstacles posed by the inclusion of oxide-sidewall spacers (common in present-day VLSI CMOS technologies) are surmountable with respect to the formation of useful buried contacts and the resultant local interconnect level that they provide. >

Localized interface trap generation in SILO-isolated MOSFETs during PECVD nitride passivation

The authors report the generation of interface traps during the plasma-enhanced chemical vapor deposition of silicon nitride passivation in MOS structures that utilize a sealed-interface local oxidation scheme (SILO) for device isolation. These traps are highly localized at the boundaries between gate and field oxides, causing enhanced subthreshold conduction. Localized interface traps of this type were not observed in identical MOS structures that use conventional LOCOS (local oxidation of silicon) isolation and were eliminated by thermal anneals at 450 degrees C. Anneals in hydrogen ambients resulted in enhanced rates of hot-carrier-induced degradation. The high densities and localized nature of these anomalous traps make possible a novel mode of device operation in which source-drain conduction is strongly modulated by substrate bias. >