Reinhard Glang

Measurement and Distribution of Faults on Defect Test Site Chips

In the development of Very Large Scale Integration (VLSI) processes, yield losses due to chip design errors and inadequate control of device parameters are usually corrected early in the development cycle. Thereafter, the yield of product chips is determined by the number of pattern defects picked up in the lengthy fabrication sequence. Monitoring defect levels associated with various process steps and reducing them systematically to achieve competitive costs remain necessary activities for as long as the product is manufactured.