Reza Kazerounian

Alternate metal virtual ground (AMG)-a new scaling concept for very high-density EPROMs

A new erasable programmable read-only memory (EPROM) array concept that reduces the cell size to the poly pitch in both directions is introduced. The key concepts that made the dramatic scaling possible are the virtual ground array with one metal line for every two diffusion bit lines, the segmentation of every other bit line, and the fieldless array. The cell size on 0.8- mu m technology is 2.56 mu m/sup 2/ and a 1- mu mm/sup 2/ cell is under development on a 0.5- mu m technology for the 64-Mb product. These cells are smaller by a factor of 2-3 than the standard EPROM cell on the same technology. The new array concept and its advantages are expandable to flash memories.<<ETX>>

Substrate injection induced program disturb-a new reliability consideration for flash-EPROM arrays

The development of high-density flash EPROMs is being directed towards scalability, sector erase, and 5-V-only operation. For the flash concepts that are utilizing channel hot electron injection for the programming, a new disturbance mechanism caused by substrate injection of thermally generated electrons is reported. This mechanism disturbs an erased call during programming cycles of other bits along the same bitline. The high-temperature programming requirement for flash EPROMs drastically enhances the disturbance through the strong increase in thermally generated electrons in the substrate. This program disturbance has the greatest impact on the wordline oriented sector erase memory architectures, through the increase in disturbance time.<<ETX>>

A bipolar load CMOS SRAM cell for embedded applications

This paper presents a new SRAM cell concept which offers cell scaling without requiring complicated, specialized processing technology. The proposed cell utilizes a bipolar transistor in an open-base (base is floating) configuration as a simple means of realizing a high impedance load element. The Bipolar Transistor Load (BTL) is designed such that its open base current (the holding current) is always large enough to compensate for the NMOS pull-down transistor leakage current. The load holding current and the pull-down transistor leakage current are based on the same physical mechanism, namely thermal generation, as a result the load exhibits current tracking properties over varying process and temperature conditions. The cell size is 72 /spl mu/m/sup 2/ with typical 0.8 /spl mu/m design rules, which is about a 60% reduction as compared to a standard 6-T full CMOS cell. The operating properties of the BTL cell were studied analytically and characterized experimentally. The BTL SRAM module can be easily integrated as part of any CMOS process with minimal additional processing steps.<<ETX>>