Reza Sotudeh

Comparative Evaluation of Hypermesh and Multi-stage Interconnection Networks

In a multicomputer network, the channel bandwidth is greatly constrained by implementation technology. Two important constraints have been identified in the literature, each appropriate for a particular technology: wiring density limits dominate in VLSI and pin-out in multiple-chip implementations. Most existing interconnection networks are categorized as either direct or indirect (multi-stage) topologies, the mesh and binary n-cube being examples of the former category, the omega and banyan networks of the latter. This paper argues that direct networks based on hypergraph topologies have characteristics which make them particularly appropriate for use in future high-performance parallel systems. The authors have recently introduced a regular multidimensional hypergraph network, called the Distributed Crossbar Switch Hypermesh (DCSH), which has topological properties that permit a relaxation of bandwidth constraints, and which has important topological and performance advantages over direct graph networks. This paper compares the DCSH to multi-stage networks, under both VLSI and multiple-chip technological constraints. The results suggest that in both cases, with a realistic model which includes routing delays through intermediate nodes, the DCSH exhibits superior performance across a wide range of traffic loads.

Constraint-based evaluation of hypergraph and graph networks

Abstract Most of the common direct multicomputer networks, such sa the torus and binary n-cube, are based on graph topologies. This paper presents the results of a comparative analysis of these topologies with a new class of regular hypergraph topologies, called Distributed Crossbar Switch Hypermeshes (DCSHs). Taking into account relative implementation cost, the analysis considers the different channel bandwidth constraints which apply in different possible realisations, such as pure VSLI and multi-chip technologies. Furthermore, it uses realistic assumptions, that have been ignored in previous similar studies, such as the inclusion of routing delays through intermediate nodes and the use of pipeline-bit transmission to lower the effects of long wires. The analysis concludes, that in many circumstances, the hypermesh has superior performance characteristics to the torus and binary n-cube.

Communication locality in hypermeshes and tori

The torus has been a popular topology for multicomputers due to its ease of implementation. Existing networks, such as the tents, are graph topologies, where a channel connects exactly two nodes. This paper argues that hypergraph topologies, where a channel connects any number of nodes, are potential candidates for future high-performance multicomputer networks. The paper assesses the support of a multi-dimensional hypergraph, referred to as the Distributed Crossbar Switch Hypermesh (DCSH), and the torus for communication locality. The results show that DCSH is a more general structure as it supports more efficiently a wide range of traffic patterns.

An improved three-step search block-matching algorithm for low bit-rate video coding applications

An improved three-step search (ITSS) block-matching algorithm for motion estimation is described, specifically aiming towards low bit-rate video-coding applications. The method is based on the real-world image sequences characteristic of centre-biased motion vector distribution, and uses centre-biased checking point patterns and a relatively small number of search locations to perform fast block matching. The computational complexity is reduced by employing an 11/spl times/11 search window rather than the traditional 15/spl times/15 window. Simulation results are presented which show that the ITSS algorithm provides better performance at a faster speed than the well-known three-step search (TSS) algorithm and the previously developed new three-step search (NTSS) algorithm when used for low bit-rate video coding, such as in the video telephone and video conferencing.

Performance evaluation of hypermeshes and meshes with wormhole routing

Abstract The hypercube, which vas widely used in early multicomputers, has fallen out of favour to be replaced by the 2-dimensional mesh or torus in recent multicomputers. This move was mainly influenced by Dailys study that has shown that for an equal implementation cost in VLSI the low-dimensional high-diameter mesh or torus has superior performance characteristics to the higher-dimensional low-diameter hypercube. Common networks such as the mesh, torus, and hypercube are graph topologies where a channel connects exactly two nodes. This paper argues that hypergraph topologies, where a channel can connect more than two nodes, represent a potential candidate for future high-performance multicomputer networks. A comparative analysis of a regular multi-dimensional hypergraph, referred to as the Distributed Crossbar Switch hypermesh (DCSH), and the mesh shows that the DCSH provides better performance for equal implementation costs in various technologies (e.g. VLSI and multiple-chip technology).

Improved multimedia server I/O subsystems

The main function of a continuous media server is to concurrently stream data from storage to multiple clients over a network. The resulting streams will congest the host CPU bus, reducing access to the systems main memory, which degrades CPU performance. The purpose of this paper is to investigate ways of improving I/O subsystems of continuous media servers. Several improved I/O subsystem architectures are presented and their performances evaluated. The proposed architectures use an existing device, namely the Intel i960RP processor. The objective of using an I/O processor is to move the stream and its control from the host processor and the main memory. The ultimate aim is to identify the requirements for an integrated I/O subsystem for a high performance scalable media-on-demand server.

A new single-bit feedback congestion scheme for ATM networks

The design of efficient congestion control mechanisms is critical to the successful use of ATM networks for the transport of multimedia traffic. Several mechanisms, based on feedback control, have been recently proposed in the literature, where the feedback information is a single-bit carried in the cell header for source rate adaptation. This paper proposes a new single-bit feedback scheme that can convey congestion information, e.g. queue(s) size and link(s) utilisation at the switches, more accurately than existing similar ones, and without extra implementation cost. Results from both theoretical analysis and simulation are presented to demonstrate its higher degree of accuracy.

Continuous discrete-event simulation of a continuous-media server I/O subsystem

When designing computer systems, simulation tools are used to imitate a real or proposed system. Complex, dynamic systems can be simulated without the cost and time constraints involved with real systems. Experimentation with the simulation enables the system characteristics to be rapidly explored and system performance data to be generated, so encouraging modification to improve performance. This paper details the experiences encountered when designing and building a proprietary continuous discrete-event object-oriented simulation in order to further investigate the performance of a proposed continuous-media server I/O subsystem. Previous investigations of the proposed architecture have been based upon mathematical models in order to calculate comparative performance. However such static models do not take into account the dynamic properties of a system. A simulation tool was therefore built in order to assess quality of service under high system load conditions. The resulting simulation rapidly produced more realistic performance figures, in addition to providing a flexible simulator infrastructure for other unrelated projects.

A Flexible VLSI Parallel Processing System for Block-Matching Motion Estimation in Low Bit-Rate Video Coding Applications

In this paper, we design a flexible VLSI-based parallel processing system for an improved three-step search (ITSS) motion estimation algorithm that is superior to the existing three-step search (TSS) algorithm in all cases and also to the recently proposed new three-step search (NTSS) algorithm if used for low bit-rate video coding, as with the H.261 standard. Based on a VLSI tree processor and an FPGA addressing circuit, the proposed architecture can successfully implement the ITSS algorithm on silicon with the minimum number of gates. Because of the flexibility of the architecture, it can also be extended to implement other three-step search algorithms.

Packetization and cell-loss concealment for MPEG-2 video transport over ATM networks

Early re-synchronization technique is a useful method to develop the error free video data in the cells after a lost cell or a transmission error. In this paper, we propose a method in which the MPEG-2 video data is packetized into cells, and the first macroblock in each cell is always located at a special bit, such as an odd bit. Hence, the early re-synchronization method can be improved to halve the computational complexity, while increasing bit-stream data content by only 13 percent. This is because the decoder will not waste its time to decode the macroblock by starting at an even bit. Furthermore, the probability of mis-decoding the macroblock can also be reduced by 50 percent. We also propose another method to utilize the start code in a cell to help correctly decoding the macroblocks located before it. Basic theoretical analysis is presented in the paper to prove that the proposed method is more effective than the existing one. The result show that the effectiveness of the re-synchronization method can be greatly improved by adopting the proposed packetizing technique.