Rhishikesh Limaye

Correct and non-defensive glue design using abstract models

Current hardware design practice often relies on integration of components, some of which may be IP or legacy blocks. While integration eases design by allowing modularization and component reuse, it is still done in a mostly ad hoc manner. Designers work with descriptions of components that are either informal or incomplete (e.g., documents in English, structural but non-behavioral specifications in IP-XACT) or too low-level (e.g., HDL code), and have little to no automatic support for stitching the components together. Providing such support is the glue design problem. This paper addresses this problem using a model-based approach. The key idea is to use high-level models, such as dataflow graphs, that enable efficient automated analysis. The analysis can be used to derive performance properties of the system (e.g., component compatibility, throughput, etc.), optimize resource usage (e.g., buffer sizes), and even synthesize low-level code (e.g., control logic). However, these models are only abstractions of the real system, and often omit critical information. As a result, the analysis outcomes may be defensive (e.g., buffers that are too big) or even incorrect (e.g., buffers that are too small). The paper examines these situations and proposes a correct and non-defensive design methodology that employs the right models to explore accurate performance and resource trade-offs.

Static dataflow with access patterns: semantics and analysis

Signal processing and multimedia applications are commonly modeled using Static/Cyclo-Static Dataflow (SDF/CSDF) models. SDF/CSDF explicitly specifies how much data is produced and consumed per firing during computation. This results in strong compile-time analyzability of many useful execution properties such as deadlock absence, channel boundedness, and throughput. However, SDF/CSDF is limited in its ability to capture how data is accessed in time. Hence, using these models often leads to implementations that are suboptimal (i.e., use more resources than necessary) or even incorrect (i.e., use insufficient resources). In this work, we advance a new model called Static Dataflow with Access Patterns (SDF-AP) that captures the timing of data accesses (for both production and consumption). This paper formalizes the semantics of SDF-AP, defines key properties governing model execution, and discusses algorithms to check these properties under correctness and resource constraints. Results are presented to evaluate these analysis algorithms on practical applications modeled by SDF-AP.

Tokens vs. Signals: On Conformance between Formal Models of Dataflow and Hardware

Designing hardware often involves several types of modeling and analysis, e.g., in order to check system correctness, to derive performance properties such as throughput, to optimize resource usages (e.g., buffer sizes), and to synthesize parts of a circuit (e.g., control logic). Working directly with low-level hardware models such as finite-state machines (FSMs) to answer such questions is often infeasible, e.g., due to state explosion. Instead, designers often use dataflow models such as SDF and CSDF, which are more abstract than FSMs, and less expensive to use since they come with more efficient analysis algorithms. However, dataflow models are only abstractions of the real hardware, and often omit critical information. This raises the question, when can one say that a certain dataflow model faithfully captures a given piece of hardware? The question is of more than simply academic interest. Indeed, as illustrated in this paper, dataflow-based analysis outcomes may sometimes be defensive (e.g., buffers that are too big) or even incorrect (e.g., buffers that are too small). To answer the question of faithfully capturing hardware using dataflow models, we develop a formal conformance relation between the heterogeneous formalisms of (1) finite-state machines with synchronous semantics, typically used to model synchronous hardware, and (2) asynchronous processes communicating via queues, used as a formal model for dataflow. The conformance relation preserves performance properties such as worst-case throughput and latency.

On Tokens and Signals: Bridging the Semantic Gap between Dataflow Models and Hardware Implementations

Dataflow models serve as useful abstractions of digital hardware in signal processing and other application domains. But when can one say that a certain dataflow model faithfully captures a given piece of hardware? To answer this question we develop a formal conformance relation between the heterogeneous formalisms of (1) finite state machines with synchronous semantics, used to model hardware, and (2) asynchronous processes communicating via queues, used as a formal model for dataflow. The conformance relation preserves performance properties such as worst-case throughput and latency.

Specification of precise timing in synchronous dataflow models

This paper proposes an extension to dataflow models with timing specifications to facilitate the construction of deterministic, platform independent, precisely timed models of software in cyber-physical systems (CPS). Dataflow models are often used to describe the software/cyber part of a CPS, owing to their succinct and analyzable representation of computation and concurrency. To capture the interaction of the cyber with the physical part, it is common practice to augment the dataflow model with nodes to represent physical sensors and actuators and handle the timing outside the dataflow model. However, the precise timing of these interactions is critical to the overall application behavior, and conventional dataflow models do not capture these timing requirements. In this work, we introduce timing configurations in dataflow models to specify when this communication between cyber and physical parts takes place. Timing specifications are derived from application requirements which are independent of the platform execution behavior. A correct implementation must fulfill the dataflow and timing requirements. This paper discusses the extension of the well-studied Synchronous Dataflow (SDF) model with timing configurations, shows how traditional SDF analysis for consistency and deadlock freedom is adapted for this model, and discusses hierarchical composition and analysis of composite SDF nodes with timing configurations. We believe that a model for the cyber part of a CPS must allow for the specification of application timing behavior as an integral part of the model. Timing extensions for dataflow models accomplish this in a natural and comprehensible manner. By illustrating timing configurations for SDF, we lay the groundwork for their application to a variety of dataflow models.

Modeling, Analysis, and Implementation of Streaming Applications for Hardware Targets

Application advances in the signal processing and communications domains are marked by an increasing demand for better performance and faster time to market. This has motivated model-based approaches to design and deploy such applications productively across diverse target platforms. Dataflow models are effective in capturing these applications that are real-time, multi-rate, and streaming in nature. These models facilitate static analysis of key execution properties like buffer sizes and throughput. There are established tools to generate implementations of these models in software for processor targets. However, prototyping and deployment on hardware targets, in particular reconfigurable hardware such as FPGAs, are critical to the development of new applications. FPGAs are increasingly used in computing platforms for high performance streaming applications. They also facilitate integration with real physical I/O by providing tight timing control and allow the flexibility to adapt to new interface standards. Existing tools for hardware implementation from dataflow models are limited in their ability to combine efficient synthesis and I/O integration and deliver realistic system deployments. To close this gap, we present the LabVIEW DSP Design Module from National Instruments, a framework to specify, analyze, and implement streaming applications on hardware targets. DSP Design Module encourages a model-based design approach starting from streaming dataflow models. The back-end supports static analysis of execution properties and generates implementations for FPGAs. It also includes an extensive library of hardware actors and eases third-party IP integration. Overall, DSP Design Module is an unified design-to-deployment framework that translates high-level algorithmic specifications to efficient hardware, enables design space exploration, and generates realistic system deployments. In this chapter, we illustrate the modeling, analysis, and implementation capabilities of DSP Design Module. We then present a case study to show its viability as a model-based design framework for next generation signal processing and communications systems.

Early timing estimation for system-level design using FPGAs (abstract only)

FPGA devices provide flexible, fast, and low-cost prototyping and production solutions for system design. However, as the design complexity continues to rise, the design and synthesis iterations become a labor intensive and time consuming ordeal. Consequently, it becomes imperative to raise the level of abstraction for FPGA designs, while providing insight into performance metrics early in the design process. In particular, an important design time problem is to determine the maximum clock frequency that a circuit can achieve on a specific FPGA target before full synthesis and implementation. This early quantification can greatly help evaluate key design characteristics without reverting to tedious runs of the full implementation flow. In this work, we focus on the predictability of timing delay of circuits composed of high-level blocks on an FPGA. We are well aware of difficulties in tackling uncertainties in early timing estimation, e.g., an inherent gap between a high-level representation and gates/wires; extremely difficult delay estimation due to the randomness in physical design tools, etc. We show that the estimation uncertainties can be mitigated through a carefully characterized timing database of primitive building blocks and refined timing analysis models. We primarily focus on applications composed of data-intensive word-level arithmetic computations from the DSP domain and specified using static dataflow models. Our experiments indicate that for these applications, timing estimates can be obtained reliably within a good error margin on average and in the worst case. As future work, we plan to fine tune the timing database by modeling resource utilization effects and inter-primitive/actor routing delay via variants of Rents rule and related efforts. We are also interested in exploring dynamic sub-cycle timing characterization.