Rhonda Franklin Drayton

Development of self-packaged high frequency circuits using micromachining techniques

A new concept for packaging high frequency monolithic circuits is presented. It consists of developing miniaturized housings to shield individual passive components (e.g., CPW based), active elements, or combinations of them by employing silicon micromachining technology. At high frequencies, self-packaged configurations that are fabricated in this manner provide reduction in the overall size and weight of a circuit and provide increased isolation between neighboring circuits. Therefore, the resulting characteristics make these micropackaged components appropriate for high density, multilevel interconnect circuits. This paper will describe the fabrication procedures used to develop self-packaged components. Performance curves for typical high frequency circuit geometries that are implemented in this configuration are shown for measured and theoretical results. >

Micromachined circuits for millimeter- and sub-millimeter-wave applications

Two approaches for the development of micromachined circuits for millimeter- and submillimeter-wave applications are discussed. These technologies provide a means to overcome the drawbacks typically associated with conventional planar transmission lines, such as microstrip and coplanar waveguides. Examples demonstrating the use of micromachining to effectively incorporate a third dimension into the geometry of monolithic circuits are presented. This introduces additional parameters in the design and results in structures with superior electrical performance, such as membrane-supported circuits, and reduced volume and weight, such as micromachined-shielded circuits. Micromachined circuits which incorporate miniaturized shielding packages in a monolithic design are described. The performance of these circuits shows that the low-volume, low-weight packaging is effective in reducing signal loss, without degrading the desired frequency response.<<ETX>>

Congratulations to the 2005 MTT-S Undergraduate/Pregraduate Scholarship Awardees!

2006 MTT-S Undergraduate/Pre-graduate Scholarships Announcement The Microwave Theory and Techniques Society is pleased to announce the Undergraduate/Pregraduate Scholarship competition for the 2006 academic year. The Undergraduate Scholarship program was instituted with the purpose of attracting undergraduate students to the microwave/RF discipline, and encouraging them to pursue graduate studies in this field. MTT-S awards up to ten

Fabrication and modeling of silicon-embedded high-Q inductors

1500 (USD) scholarships each academic year. In addition, travel expenses are reimbursed for recipients to travel to an MTT-S-sponsored conference up to

Micromachined filters on synthesized substrates

1000 (USD) per awardee. Requirements. Applicants must be an undergraduate student in electrical engineering (or related field) at the time of application, but may be enrolled in his/her final year of the undergraduate program, first year of graduate studies, or combined B.S./M.S. program during the academic year for which the scholarship is awarded. Selection criteria include academic performance, a proposal for project work and career goals in the microwave/RF area and a faculty mentor recommendation. There are no U.S. citizenship requirements; awards are distributed globally. The applicants must be IEEE student members and their faculty mentors must be IEEE MTT-S Members. The deadline for applications is typically May 1st of the award cycle year. Awardees are selected by a team of experts who are also MTT Society members. More details are available from the IEEE MTT-S Web page at http://www. mtt.org—click on Awards > Undergraduate Scholarships; or contact Prof. Rhonda Franklin Drayton at drayton@umn.edu Professor Drayton chairs the Undergraduate/Pre-Graduate Scholarship program on behalf of the MTT-S AdCom Education Subcommittee.

Porosity effects on coplanar waveguide porous silicon interconnects

In this paper, we report on the fabrication and modeling of a CMOS-compatible silicon-embedded high-Q integrated inductor (µH range). The fabrication process is based on DRIE, pulse-reverse super-conformal electroplating of copper and chemical–mechanical polishing. A lumped-element equivalent circuit model based on electromagnetic finite-element simulations for the determination of the element values was also developed. Inductors with different geometric design parameters were simulated to show the optimization possibility using the model. A Q-factor of over 60 (at 30–40 MHz) for a 2 µH inductor was measured, which is the highest reported in the literature for integrated inductors at such frequencies. The measurement results closely match the simulations from the lumped circuit model.

Micromachined low dispersion interconnects for optoelectronic array packaging

Effective frequency spectrum usage requires high performance filters with a sharp cut-off frequency and high stopband attenuation. Stepped impedance lowpass designs achieve this with large ratios of high and low impedance values. In high index materials, however, such as Si (11.7) and GaAs (12.9), these ratios are around 5 which significantly limit filter performance. This paper presents the use of Si micromachining to produce synthesized substrates with stepped-impedance low filter designs. Of the two designs, one offers a reduction of the low impedance value while the other offers an increase of the high impedance value to produce Z/sub H//Z/sub L/ ratios that are 1.5 to 2 times larger than conventional designs.

Aperture coupled patch antenna chip performance on lossy silicon substrates

Oxidized porous silicon (OPS) has the potential to produce low loss designs for high-density RF passive and CMOS integrated circuits. Herein are findings on porosity effects on finite ground coplanar waveguide (FGCPW) lines printed on OPS material up to 50 GHz. At 51% porosity, measured effective dielectric constant data (/spl epsi//sub r,eff/) is approximately 2.8 and is consistent with Bruggeman models. For similar low (low-rho) and high (high-rho) resistivity silicon designs, OPS attenuation (dB/cm) exhibits 78% less loss than low-rho designs with 1.5 and 9.5% less than and greater than, the high-rho design at 10 and 20 GHz, respectively. Furthermore, wideband 50-ohm impedance matching is achieved. These findings, therefore, support consideration of oxidized porous silicon for RFIC design.

Fabrication and modeling of silicon-embedded high Q inductors

A micromachined microstrip interconnect, partially shielded on the top surface, is designed, fabricated, and measured for use in optical array packaging applications. Field simulations show the interconnects to be highly isolated for an array pitch of 500 /spl mu/m. S-parameter, relative phase constant, and attenuation curves are shown up to 40 GHz for 1 cm long 50-ohm designs. The structure exhibits 1.4 dB/cm of attenuation at 40 GHz and a phase constant that has only /spl plusmn/ 0.5% variation across the band. The micromachined partially shielded microstrip offers high isolation, low dispersion, and low attenuation that is necessary for arrayed interconnects.

DC bias effects on bulk silicon and porous silicon substrates

A 15 GHz aperture coupled patch antenna with its feed line on porous silicon is demonstrated. The measured and simulated return loss results show a resonant frequency of 14.7 and 14.8 GHz respectively and bandwidths of 0.7 and 1 GHz. Simulated radiation patterns show an antenna with a high front to back ratio