Richa Barsainya

Design of minimum multiplier fractional order differentiator based on lattice wave digital filter.

In this paper, a novel design of fractional order differentiator (FOD) based on lattice wave digital filter (LWDF) is proposed which requires minimum number of multiplier for its structural realization. Firstly, the FOD design problem is formulated as an optimization problem using the transfer function of lattice wave digital filter. Then, three optimization algorithms, namely, genetic algorithm (GA), particle swarm optimization (PSO) and cuckoo search algorithm (CSA) are applied to determine the optimal LWDF coefficients. The realization of FOD using LWD structure increases the design accuracy, as only N number of coefficients are to be optimized for Nth order FOD. Finally, two design examples of 3rd and 5th order lattice wave digital fractional order differentiator (LWDFOD) are demonstrated to justify the design accuracy. The performance analysis of the proposed design is carried out based on magnitude response, absolute magnitude error (dB), root mean square (RMS) magnitude error, arithmetic complexity, convergence profile and computation time. Simulation results are attained to show the comparison of the proposed LWDFOD with the published works and it is observed that an improvement of 29% is obtained in the proposed design. The proposed LWDFOD approximates the ideal FOD and surpasses the existing ones reasonably well in mid and high frequency range, thereby making the proposed LWDFOD a promising technique for the design of digital FODs.

Minimum multiplier implementation of a comb filter using lattice wave digital filter

The minimum hardware and low power dissipation are the main concern for efficient filter implementation. A method to design and implement the comb lattice wave digital filter with only one multiplier, small area and low power dissipation is proposed. Lattice wave digital filter is used for filter realization due to its excellent properties. A design level area optimization is done by converting constant multipliers into shifts and adds using canonical signed digit code (CSDC) technique. The filter is implemented and successfully tested on Xilinx Spartan XC3s200-4ft256 field programmable gate array (FPGA) device. The effectiveness of the proposed design method is proven with an example.

Novel wave digital equivalents of passive elements

The wave digital equivalent of passive elements using wave theory and bilinear transform is formulated in yesteryear, but the bilinear transform produces large distortion in the mid and high frequency range. In this paper, a novel wave digital equivalents of analog passive elements are developed. Instead of bilinear transform, two different transforms are used for analog to digital (A/D) conversion in order to overcome the limitation of the aforementioned transform. The comparison of transforms along with the resultant wave digital equivalents of passive elements using these transforms and wave theory is introduced. In this paper, it is also considered that practically, analog elements are not ideal, but leaky. So, wave digital equivalents of leaky analog elements are also proposed.

Design and implementation of fractional order integrator with reduced hardware

This paper proposes a novel methodology for design and multiplierless implementation of fractional order integrator (FOI) based on lattice wave digital filter using gravitational search algorithm (GSA). The FOI design problem is formulated as an optimization problem using the transfer function of lattice wave digital filter (LWDF). The realization of FOI using LWDF structure increases the accuracy of design due to its excellent properties and also it requires only N number of multiplier coefficients for Nth order FOI. Furthermore, the minimum hardware and low power dissipation of FOI, which are the main concern of efficient implementation is also presented in this paper. The design level area optimization of the proposed lattice wave digital FOI (LWDFOI) is done by converting constant multipliers into shifts and adds using canonical signed digit code (CSDC) technique. The proposed LWDFOI is implemented and successfully tested on Xilinx Spartan XC3s200-4ft256 field programmable gate array (FPGA) device. Simulation results are accomplished to show the comparison of the proposed LWDFOI with recent literature. The performance of the proposed LWDFOI is also evaluated in terms of speed, i.e. maximum frequency, area (number of slices) and power consumption. The proposed LWDFOI have been found to outperform the existing ones reasonably well in low and mid frequency range.

Multiplier-less implementation of quadrature mirror filter

The minimum hardware and low power dissipation have always been the main concern for the efficient filter implementation. In this paper, an efficient way of implementing the lattice wave digital filter (LWDF) structure of the quadrature mirror filter (QMF) with canonic signed digit (CSD) coefficients is proposed. Further, the proposed structure is implemented using carry save adders rather than slow carry propagation adders. This increases the speed of the overall filter structure compared to the conventional way of implementing the filter with CSD coefficients. The proposed QMF is implemented and successfully tested on Xilinx Spartan XC3s200-4ft256 field programmable gate array (FPGA) device. The effectiveness of the proposed design method is proven with an example.

FPGA implementation of Hilbert transformer based on lattice wave digital filters

The minimum hardware and low power dissipation have always been the main concern for the efficient filter implementation. In this paper, an effective way of implementing the lattice wave digital structure of the Hilbert transformer with canonic signed digit code (CSDC) coefficients is proposed. Further, the proposed structure is implemented using carry save adders rather than slow ripple carry adders. This increases the speed of overall filter structure compared to the conventional way of implementing the filter with CSDC coefficients. The proposed Hilbert transformer is implemented and successfully tested on Xilinx Spartan XC3s200-4ft256 field programmable gate array (FPGA) device. The effectiveness of the proposed design method is proven with an example.

Low power reconfigurable Hilbert transformer design with row bypassing multiplier on FPGA

Reconfigurability and low power have always been the main concern for the efficient filter implementation. This paper introduces two new low power and high speed reconfigurable Hilbert transformer designs. These designs are based on the carry save adder (CSA) and ripple carry adder (RCA) based row bypassing multipliers. The primary power reduction is procured by turning off adders when the multiplier operands are zero. In addition, the proposed Hilbert transformers are implemented with parallel architecture of multipliers to shorten the delay time. The proposed designs can be dynamically reconfigured with arbitrary coefficients that are only limited by their length and word size. These Hilbert transformers have been implemented and tested on Vertex-IV field programmable gate array (FPGA) board. The effectiveness of the proposed design method is presented with an example. The performance of both the designs is evaluated in terms of area (number of slices), speed, i.e., maximum frequency and power consumption. The results depict that the CSA row bypassing multiplier based Hilbert transformer achieves 17% increase in speed and 13% area reduction in comparison with RCA row bypassing multiplier based Hilbert transformer. While the power dissipation of the later transformer is 65% less than the former one.

Implementation of low power reconfigurable parametric equalizer with row bypassing multiplier on FPGA

For the efficient filter implementation reconfigurability and low power have always been the main concerns. This paper introduces two new low power and high speed reconfigurable parametric equalizer designs. These designs are based on the row bypassing multipliers which are implemented using carry save adder (CSA) and ripple carry adder (RCA). The primary power reduction is procured by turning off adders when the multiplier operands are zero. In addition, the proposed equalizers are implemented with parallel architecture of multipliers to shorten the delay time. The proposed designs can be dynamically reconfigured with erratic coefficients that are only constrained by their order and coefficient world length. These parametric equalizers have been implemented and tested on Vertex-IV field programmable gate array (FPGA) board. The efficacy of the proposed design method is presented with an example. The performance of both the designs is evaluated and compared in terms of area (number of slices), speed, i.e., maximum frequency and power consumption. The results depict that the CSA row bypassing multiplier based parametric equalizer achieves 11% speed enhancement and 18% area reduction in comparison with RCA row bypassing multiplier based parametric equalizer. While the power dissipation of the later equalizer is 5% less than the former one.

Wave Digital Realization of Current Conveyor Family

The wave digital equivalents of various passive and active elements using wave theory were formulated in yesteryears. Current conveyors have received considerable attention in present scenario. A generalized current conveyor (GCC) represents 12 concrete current conveyors. In this paper, 12 wave digital equivalent circuits of a generalized current conveyor are presented which can further be utilized for the development of a new class of wave digital filters.

Optimal Design of Minimum Multiplier Lattice Wave Digital Lowpass Filter using Metaheuristic Techniques

This study aims towards the efficient design of arbitrary-band and halfband lowpass (LP) filter based on lattice wave digital filter (LWDF) structure with the usage of minimal number of multipliers in its structural realisation. The designing of the LP filter is formulated as an optimisation problem where coefficients of LWDF transfer function are iteratively optimised by the evolutionary algorithms. The potential of four optimisation algorithms, real-coded genetic algorithm, particle swarm optimisation, differential evolution algorithm, and cuckoo search algorithm, are explored for determining the optimal LWDF coefficients by minimising the error objective function. The structural realisation of LP using LWDF structure enhances the design accuracy as the usage of multiplier prominently reduces. The simulation and statistical results of the proposed lattice wave digital lowpass filter (LWDLF) and bireciprocal lattice wave digital lowpass filter (BLWDLF) design show significant improvement in the mean square error, passband ripples, transition bandwidth, stopband attenuation, rate of convergence, and execution time. To manifest the efficient design of the proposed LWDLF and BLWDLF, the results are compared with the designed arbitrary-band, halfband canonic-LP filters and previous published works.