Richard C. Shen

MPEG-2 video decoder for the digital HDTV Grand Alliance system

A real-time video decoder which can decompress an MPEG-2 video bitstream having a bitrate up to 45 Mb/s is described. The decoder, which can operate at HDTV pixel rates, was built as part of the Grand Alliance (GA) HDTV system. It is currently undergoing testing by the Advisory Committee on Advanced Television Service (ACATS). The hardware converts encoded bitstreams into displayable video signals. Various video and film frame rates are supported, and switching between all format and frame rate combinations is accomplished seamlessly. This paper describes the GA video decoder hardware architecture and implementation. >

Digital video and the national information infrastructure

Abstract This paper gives an overview of the efforts in the United States to build high-speed networks for the delivery of digital video services to the homes of consumers. It details the obstacles that need to be overcome for digital video service to commence and the various network architectures and technologies that have been, and presently are being considered. The applications are described that will be enabled by such an infrastructure, termed the NII, as are two digital video services oriented market trials — one being conducted by a cable operator and the second by a telephone company.

Grand alliance MPEG‐2‐based video decoder with parallel processing architecture

A practical and unique hardware architecture for video bitstream source decoding and video postprocessing of a Moving Pictures Expert Group (MPEG‐2)‐based high‐definition television (HDTV) compressed bitstream has been implemented to impose minimal limitations on the video source coding algorithm. The Grand Alliance (GA) MPEG‐2‐based HDTV codec achieves a high degree of source and channel coding efficiency while preserving the delivery of high‐resoultion picture quality in a variety of video input and output formats in bandwidth‐limited channels. The video source decoder hardware architecture necessary to achieve the data decoding and ensuing video postprocessing poses numerous technologic challenges to the system designer, who must tradeoff minimizing codec constraints with the eventual commercialization of a video decoder for a consumer television receiver product. The powerful and flexible coding algorithm necessary to satisfy the HDTV picture quality and transmission channel bandwidth limitation requirements results in an encoder‐output bitstream that necessitates high throughout decoding. Although the transmitted bitstream is of constant rate due to rate buffering, bistreams internal to the codec are both peaky and bursty. An intelligent distributive parallel processing decoding architecture has been developed to dynamically partition the MPEG‐2 bitstream into a number of decodable subset bitstreams, while placing minimal constraints on the encoding algorithm. This architecture allows for high‐speed, efficient decoding of the bitstream, and can be a prelude to the development of a cost‐effective consumer product. Further architecture refinements can be explored, including implementation in VLSI.