Richard D. Baertsch

A third-order multistage sigma-delta modulator with reduced sensitivity to nonidealities

A multistage third-order sigma-delta modulator, which is unconditionally stable and has a low sensitivity to component mismatch and op-amp performance limitations, has been designed and fabricated in a 1.2- mu m CMOS double-poly technology. The modulator, consisting of cascaded second- and first-order stages, is scaled to prevent performance degradation from integrator overload. In addition, the first-stage integrator output is used directly, instead of its quantization error, to facilitate ratioless input circuitry in the second stage. Experimental results indicate a signal-to-noise ratio of 93 and 90 dB at a signal-to-distortion ratio of 93 dB for sample rates of 24 and 80 kHz, respectively. >

SURFACE CHARGE TRANSPORT IN SILICON

Surface charge was successfully transported by means of a series of overlapping conductor‐insulator‐semiconductor capacitor plates. The transport mechanism involves a field‐driven diffusionlike phenomenon which is analyzed theoretically, and the results are compared to experiments performed on simple structures.

The design and operation of practical charge-transfer transversal filters

Some of the design considerations for charge-transfer split-electrode transversal filters are discussed. Clock frequency, filter length, and chip area are important design parameters. The relationship of these parameters to filter performance and accuracy is described. Both random and tap weight quantization errors are considered, and the optimum filter length is related to tap weight error. A parallel charge-transfer channel, which balances both capacitance and background charge, and a coupling diffusion between split electrodes greatly improves accuracy. A one-phase clock is used to simplify the readout circuitry. Two off-chip readout circuits are described, and the performance of two low-pass filters using these readout circuits is given. Signal to noise ratios of 90 dB/kHz and an overall linearity of 60 dB have been achieved with this readout circuitry.

Gamma Ray Detectors Made from High Purity Germanium

A solution regrowth technique for growing P+ and N+ contacts on high purity germanium is described. Copper contamination of the high purity germanium is minimized by using KCN to remove copper from the surface of the germanium and by the gettering ability of molten indium in contact with the germanium. Diodes with leakage currents as low as 3 × 10-11 amp for 2000 volts applied to a fully depleted 4 mm thick detector have been fabricated. Preliminary measurements show that the resolution obtained with these diodes is comparable to the best Li drifted germanium detectors at 60 keV and 122 keV. Diodes have been warmed to room temperature as many as five times with no degradation in resolution.

A 32-channel charge readout IC for programmable, nonlinear quantization of multichannel detector data

A Charge Readout Integrated Circuit (CRIC) which converts detector charges to digital codes is described. The CRIC provides 32 channels of circuitry needed to form charge-to-digital converters having a total dynamic range of 17 b comprised of 4 b of pre-amp gain control and a conversion range of 13 b. Each channel includes a switched-capacitor integrator, a double-sampling amplifier, a sampling comparator, and a 12-b digital latch, forming a pipeline from which a new conversion result is readout every 50 /spl mu/s. The data conversion scheme implements a programmable compression curve, which is stored as a lookup table in an off-chip, digital memory. In addition to the lookup table, data conversion requires an off-chip digital-to-analog converter, both of which may be shared by any number of CRICs. The CRIC was fabricated using a 3-/spl mu/m, n-well BiCMOS process, and occupies a die area of 5.1 mm/spl times/7.5 mm. It operates at 10 MHz, consumes 440 mW from /spl plusmn/5-V supplies, and has a demonstrated input-referred noise performance of 2.2 /spl mu/V r.m.s., i.e., 1400 e/sup -/ on 100 pF of shunt capacitance. >

Surface‐Charge Transport in a Multielement Charge‐Transfer Structure

A two‐phase 14‐stage transfer shift register has been built and operated which uses the surface‐charge transistor structure to effect the transfer of signal charge from one stage to the next. This paper describes the structure and presents preliminary experimental results which characterize its operation as a digital shift register. The shift register is operated in both the complete and partial transfer modes. An analytical solution for the approximate equation of motion of charge under a single electrode plate has been obtained. A key result of the analytical solution is that the characteristic time for transfer of charge out of a full potential well is given by t0=L2/μ(V‐VT). A computer simulation of the 14‐stage shift register, using the analytical solution for a single stage, is in good agreement with the experimental results.

The surface-charge transistor

The surface-charge transistor (SCT) is a new active semiconductor device that can be used to store, transport, and control the transport of nonequilibrium surface charge. In its simplest (discrete) form, it consists of two adjacent storage electrodes and an overlapping control electrode. All of these electrodes are separated from each other and the semiconductor surface by a thin insulating film. This structure will provide storage and controlled transport of mobile surface charge along the semiconductor surface. Data are presented for both the quasi-static characteristics of this device and its transient response. The quasi-static data are compared with an analysis based on the solution of Poissons equation for the device, and the measured transient response is compared with a numerical solution of the equation of motion for surface-charge transport. The accuracy of these models is attested to by the agreement between theory and experiment. The fabrication of surface-charge transistor structures is also described.

A surface-charge random-access memory system

The authors present a surface-charge storage cell suitable for word-organized dynamic random-access memory and discuss its operation in a memory system. Experimental results and computer simulations of the readout process on a 4/spl times/8 array using this cell are given. A sensitive stable sense-and-refresh amplifier, suitable for use with this memory cell is also described. Simulations of a 4096-bit chip with a storage cell density of 2.5 mils/SUP 2//bit using this refresh amplifier predict a cycle time of 250 ns.

A memory system based on surface-charge transport

The surface-charge transistor (SCT) is an integrated-circuit element and involves a new concept for controlling the transfer of stored electrical charge along the surface of a semiconductor. The experimental transient response of a large-geometry SCT is presented. Linear high-density arrays of surface-charge transistors may be utilized to form digital or analog shift registers. The experimental performance of a 14-bit shift register, which has been operated in both these modes, is given. By forming these units in a serpentine fashion, charge (information) may be transported back and forth between refresh circuits to form an array of cells. An experimental circuit of this type is presented. Using these techniques a digital serial memory of high density may be constructed. Using standard metalization linewidths and tolerances a cell size of 2 mil/SUP 2/ per bit is shown to be feasible.

A charge transfer recursive filter

As all the weighting coefficients of the filter are positive, a weighted charge quantity is collected by a line beneath one of the elementary electrodes of each weighting electrode. A charge reading device is coupled to the line and supplies an electrical signal which is transmitted to the negative input of a differential amplifier, which receives the sampled input voltage of the filter at its positive input. The electrical output signal of the filter is taken, under low impedance, at the output of the differential amplifier, said signal being reinjected at the input of the filter by the injecting means.