Richard E. Haskell

Transient signal propagation in lossless, isotropic plasmas

The asymptotic behavior of transient signal propagation in lossless, isotropic plasmas is discussed for a typical input signal of a step modulated sine wave. A generalized saddlepoint integration is carried out which gives a continuous solution for the dispersed signal everywhere except at the signal wavefront. The solution which is valid at the signal wavefront is obtained by using a high-frequency expansion technique. Universal curves are presented for the behavior of the distorted signal as a function of the plasma frequency, signal frequency, and propagation distance. The solution is a good approximation for the case of plasma propagation lengths which are long compared to a free space wavelength and for the operating frequency near the plasma frequency. This solution is useful since the available exact solutions for this case converge too slowly to be practically computed.

Accelerating the performance of particle swarm optimization for embedded applications

The ever increasing popularity of particle swarm optimization (PSO) algorithm is recently attracting attention to the embedded computing world. Although PSO is in general considered to be computationally efficient algorithm, its direct software implementation on complex problems, targeted on low capacity embedded processors could however suffer from poor execution performance. This paper first evaluates the performance of the standard PSO algorithm on a typical embedded platform (using a 16-bit microcontroller). Then, a modular, flexible and reusable architecture for a hardware PSO engine, for accelerating the algorithms performance, will be presented. Finally, implementation test results of the proposed architecture targeted on Field Programmable Gate Array (FPGA) technology will be presented and its performance compared against software executions on benchmark test functions.

Enhancing performance of PSO with automatic parameter tuning technique

Particle Swarm Optimization (PSO) has gained growing popularity in the recent years and is finding a wide range of important applications. Like other population based, stochastic meta-heuristics, PSO has a few algorithm parameters that need to be carefully set to achieve best execution results. This paper develops an automatic parameter tuning technique for enhancing its performance. The effectiveness of the proposed method is demonstrated on mathematical benchmark functions as well as on a real world application problem.

Multi-swarm parallel PSO: Hardware implementation

The ever increasing popularity of the particle swarm optimization (PSO) algorithm is recently attracting attention to the embedded computing world. Although PSO is considered efficient compared to other contemporary population based optimization techniques, for many continuous multimodal and multidimensional problems, it still suffers from performance loss when it is targeted onto embedded application platforms. Examples of such target applications include small mobile robots and distributed sensor nodes in sensor network applications. In a previous work we presented a novel, modular, efficient and portable hardware architecture to accelerate the performance of the PSO for embedded applications. This paper extends the work by presenting a parallelization technique for further speedup of the PSO algorithm by dividing the swarm into a set of subswarms that are executing in parallel. The underlying communication topology and messaging protocols are described. Finally, the performance of the proposed system is evaluated on mathematical and real-world benchmark functions.

A VHDL Forth Core for FPGAs

Abstract The Forth programming language is typically implemented to run on some particular microprocessor. Several Forth engines have been designed that execute Forth instructions directly, typically in a single clock cycle. With the advent of high density FPGAs it has become feasible to implement a high-performance Forth core in an FPGA. This paper describes the design of a Forth core using VHDL that has been implemented on a Xilinx Spartan II FPGA. Examples are presented of high-level Forth programs that are compiled to VHDL code that implements a ROM embedded in the FPGA. The use of a Forth core in an FPGA allows for rapid prototyping of digital systems. Experiments show that an identical Forth program for the Sieve of Eratosthenes executes nearly 30 times faster on the FPGA Forth core than on a 68HC12 microcontroller at the same clock speed. This same program executes over six times faster on the FPGA Forth core than an equivalent compiled C program run on the same 68HC12. The Forth core is available as an EDIF file at www.tigs.com/fc16 , which can be included in a VHDL project and uses approximately 30% of a Spartan II FPGA.

A modular and efficient hardware architecture for particle swarm optimization algorithm

Particle Swarm Optimization (PSO), a population based optimization algorithm, has recently been attracting the attention of the embedded computing community. It is an efficient tool for many continuous multimodal and multidimensional problem classes. This paper first evaluates the performance of the PSO algorithm on embedded processor platforms with limited computational resources. The results on such platforms demonstrate the lack of sufficient execution speed for real-time applications. Thus, to address the shortcomings of the software PSO we developed a hardware architecture that significantly accelerates its execution performance. Besides improving the execution efficiency, the design is shown to be modular, flexible and reusable for solving different optimization problems. The accelerated execution performance of the proposed architecture is demonstrated on standard mathematical benchmark functions as well as on a real world problem scenario: emission source localization in distributed sensor networks. A parallelization scheme for further speed-up of the hardware PSO is also demonstrated.

Flowpaths: Compiling stack-based IR to hardware

Abstract The performance of software executed on a microprocessor is adversely affected by the basic fetch–execute cycle. A further performance penalty results from the load–execute–store paradigm associated with the use of local variables in most high-level languages. Implementing the software algorithm directly in hardware such as on an FPGA can alleviate these performance penalties. Such implementations are normally developed in a hardware description language such as VHDL or Verilog. More recently, several methods for using C as a hardware description language and for compiling C programs to hardware have been researched. Several software-programming languages compile to an intermediate representation (IR) that is stack based such as Java to Java bytecodes. Forth is a programming language that minimizes the use of local variables by exchanging the load–execute–store paradigm for stack manipulation instructions. This paper introduces a new systems architecture for FPGAs, called flowpaths, which can implement Java bytecodes or software programs written in Forth directly in an FPGA without the need for a microprocessor core. In the flowpath implementation of Forth programs all stack manipulation instructions are represented as simple wire connections that take zero time to execute. In the flowpath implementation of Java bytecodes the normal load–execute–store paradigm is represented as a single sequential operation and stack-manipulation operations become combinational thus executing faster. This paper compares the use of flowpaths in an FPGA generated from Java bytecodes and a high-level Forth program for the Sieve of Eratosthenes with C, Java, and Forth executed on microprocessors and microprocessor cores on FPGAs. The results show that flowpaths perform within a factor of two of a minimal hand-crafted direct hardware implementation of the Sieve and orders of magnitude better than compiling the program to a microprocessor.

Geno-fuzzy classification trees

Making the non-terminal nodes of a binary tree classifier fuzzy can mitigate tree brittleness. Using a genetic algorithm, two optimization techniques are explored. In one case, each generation minimizes classification error by optimizing a common fuzzy percent, pT, used to determine parameters at every node. In the other case, each generation yields a sequence of minimized node-specific parameters. The output value is determined through defuzzification after input vectors, in general, take both paths at each node with a weighting factor determined by the node membership functions. Experiments conducted using this geno-fuzzy approach yield an improvement compared with other classical algorithms.

FPGA integrated co-design

The main problem in hardware/software co-design is how to design an embedded system that contains both hardware in the form of FPGAs or ASICs and a microprocessor for which software must be written. A critical decision that has a profound effect on overall system cost is how to partition the system into its hardware and software components. A mistake made in this decision, which must be corrected by reworking the entire design, can add significant delay and cost to the design process. The longer the irrevocable decision of how to partition the hardware and software can be delayed, the better is the chance to keep overall system cost to a minimum. This paper describes an approach that has been tested in a graduate course on FPGA design that will allow the hardware/software partition decision to be delayed to the very end of the design process.

Nomographs for Holographic Imaging

Nomographs for point source holographic imaging, discussing recording and reconstruction geometry