Richard H. Scales | Researchain

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Archive | 2001

Loop cache memory and cache controller for pipelined microprocessors

Richard H. Scales

Archive | 1998

Interruptable multiple execution unit processing during operations utilizing multiple assignment of registers

Eric J. Stotzer; Richard H. Scales

international symposium on microarchitecture | 2001

Controlling code size of software-pipelined loops on the tms320c6000 vliw dsp architecture

Elana D. Granston; Richard H. Scales; Eric J. Stotzer; Andrew Ward; Joe Zbiciak

Archive | 2000

Microprocessor with an instruction immediately next to a branch instruction for adding a constant to a program counter

Alan L. Davis; Richard H. Scales; Natarajan Seshan; Eric J. Stotzer; Reid E. Tatge

Archive | 2000

Microprocessor with instructions for shifting data responsive to a signed count value

David Hoyle; Richard H. Scales; Min Wang; Joseph Zbiciak

Archive | 1999

Self-priming loop execution for loop prolog instruction

Richard H. Scales; Natarajan Seshan

Archive | 1998

A digital signal processor with peripheral devices and external interfaces

Jonathan G. Bradley; Jason Jones; Michael J. Moody; Tai H. Nguyen; Jeffrey R. Quay; Richard H. Scales; Natarajan Seshan; Laurence R. Simar; Kenneth L. Williams

Archive | 2000

Microprocessor with an instruction for multiply and left shift with saturate

Richard H. Scales

Archive | 1998

Method and apparatus for performing a shift instruction with saturate by examination of an operand prior to shifting

Richard H. Scales; Jerald G. Leach

Archive | 1998

Digital signal processor having peripheral device and external interface

Jonathan G. Bradley; Jason Jones; Michael J. Moody; Tai H. Nguyen; Jeffrey R. Quay; Richard H. Scales; Natarajan Seshan; Laurence R. Simar; Kenneth L. Williams; エル．ウィリアムズケネス; エイ．ティ．ジョーンズジェイソン; アール．クエイジェフリー; ジー．ブラドリイジョナサン; エイチ．ヌグイエンタイ; セスハンナタラジャン; ジェイ．ムーディマイケル; エイチ．スケイルズリチャード; アール．シマーローレンス

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