Richard I. Mellitz

High speed differential I/O overview and design challenges on Intel enterprise server platforms

In this paper, the high speed differential I/O buses which are used on Intel server platforms are explored. The characteristics of channel components are examined along with channel and I/O circuit design challenges. Statistical time domain and frequency domain methods are briefly discussed as start-of-art simulation tools.

Dispersion Effects from Induced Dipoles

The interaction between a charged particle and an electric field can produce a dipole moment that changes the electric permittivity, epsiv, of a material. This paper develops the real and imaginary contributions of permittivity stemming from three types of charges in propagating mediums that produce dipole moments: permanent polar molecule moments, induced atomic moments, and free electrons in the conduction bands of semiconductors and conductors. The permittivity leads to a response function for time dependent electric flux density that causes dispersion in propagating fields

Dielectric modeling, characterization, and validation up to 40 GHz

As computer speeds continue to scale with Moores law, improved transmission line modeling techniques are required for data rates greater than 3-5 gigabits per second (Gb/s). These transmission line models must accurately predict the interconnect characteristics to provide silicon designers correct channel parameters to ensure viable products. This work describes an analytic dielectric modeling methodology that produces accurate dielectric characteristics up to 40 GHz. Validation of multiple dielectric materials was performed up to 40 GHz by direct and indirect measurement techniques. The dielectric materials chosen for this study were based upon commonly available dielectrics that are suitable for high volume manufacturing in the printed wiring board industry.

An excerise in applying channel operating margin (COM) for 10GBASE-KR channel design

COM defined in IEEE Std 802.3bj-2014 is applied to the design of 10GBASE-KR channels. Derivation of COM parameters from 10GBASE-KR is discussed in the historical context of documents published during the 10GBASE-KR standard development process. A comparison exercise is performed for channels analyzed with Annex69B and COM.

Analysis of copper treatments and the effects on signal propagation

As computer data rates increase into the 30 - 50 Gb/s range fundamental material challenges emerge that make it difficult to design a robust electrical interconnect between the transmitter and receiver. This paper discusses the effects of differing copper treatments and the effects these treatments have on signal propagation for a computer electrical interconnect. Two types of treatments have been studied: high profile copper (HPC) and low profile copper (LPC). Discussions on the physical surface geometry and elemental analyses of these copper types along with their signaling effects are discussed below.

Towards a PCB production floor metric for go/no go testing of lossy high speed transmission lines

Purpose – The aim of this paper is to demonstrate that root impulse energy (RIE) testing is a practical and robust “go/no go” test technique for PCB material losses that can be deployed on the PCB production floor.Design/methodology/approach – The study used the RIE method, employing time domain reflectometry techniques on industry standard impedance test coupons modified to include short reference lines and longer test lines. Practical considerations for the use of the methodology on the production floor, such as coupon design, probe layout and environmental conditions were investigated.Findings – RIE with a 250 ps reflected risetime appears suitable for discerning significant differences in material loss properties provided proper coupon design is incorporated into the panel design and frequencies of interest are limited to a limit commensurate with high reliability and repeatability.Research limitations/implications – The RIE test proposed does not replace conventional impedance control techniques that...

New interconnect evaluation metric for high-speed IO

This paper proposes new frequency-domain (FD) metrics to evaluate and optimize interconnects for high-speed IO. In this paper, we focused on a spring-probe socket for interconnects and PCIe Gen3 for the high-speed IO. For design optimization, we adapted a holistic approach utilizing response surface methodology. Using the proposed metrics, the spring-probe socket design was optimized to minimize impact on the IO channel performance. In order to check the validity of the new metrics, an optimized socket design via voltage margin and timing margin from eye opening was compared.

PCB differential capacitor cross-talk study and design using HFSS

The speeds of computers need to increase. A limitation to increasing this speed is the layout design of printed circuit boards (PCBs). One of the critical limiting factors of the PCB is the orientation of differential capacitors with respect to one another. This paper determines the optimal orientation of these capacitors in order to reduce the return loss (DS11) from crosstalk as the speeds of computers rise to 20 GHz.

Statistical and transient channel modeling for crosstalk, bit error, jitter, and EMI

This paper describes a SerialATA 3.0 Gb/s channel created using one-, two-, and three-dimensional models. These various models have been combined with circuit simulation techniques to provide channel bit error rates (BER) under different de-emphasis settings. Analysis of the channel was performed using an aggressor-victim-aggressor simulation strategy that included Gaussian random jitter (RJ) and deterministic jitter in the form of duty cycle distortion (DCD). Finally, upon completion of the statistical solutions, various bit patterns and edge rates are chosen to act as the excitation source for near- and far-field plots on a backplane board. This technique provides an innovative simulation strategy that combines full channel analysis including radiated emissions dependent on drive strength and bit patterns.