Richard J. McPartland

Systematic error correction for multi-level flash memory

Built-in self test for memory arrays using error correction coding

Non-volatile memory cell having channel initiated secondary electron injection programming mechanism

Low voltage flash EEPROM memory cell with improved data retention

Dynamic random access memory with low-power refresh

Apparatus and method for programming a one-time programmable memory device

Semiconductor memory repair methodology using quasi-non-volatile memory

Memory built-in self-characterization

Reduced Leakage Driver Circuit and Memory Device Employing Same

Memory Device with Error Correction Capability and Efficient Partial Word Write Operation