Richard Linhart

Evidence for non-exponential elastic proton-proton differential cross-section at low |t| and √ s = 8 TeV by TOTEM

Abstract The TOTEM experiment has made a precise measurement of the elastic proton–proton differential cross-section at the centre-of-mass energy s = 8 TeV based on a high-statistics data sample obtained with the β ⁎ = 90 m optics. Both the statistical and systematic uncertainties remain below 1%, except for the t-independent contribution from the overall normalisation. This unprecedented precision allows to exclude a purely exponential differential cross-section in the range of four-momentum transfer squared 0.027 | t | 0.2 GeV 2 with a significance greater than 7 σ . Two extended parametrisations, with quadratic and cubic polynomials in the exponent, are shown to be well compatible with the data. Using them for the differential cross-section extrapolation to t = 0 , and further applying the optical theorem, yields total cross-section estimates of ( 101.5 ± 2.1 ) mb and ( 101.9 ± 2.1 ) mb , respectively, in agreement with previous TOTEM measurements.

Diamond detectors for the TOTEM timing upgrade

This paper describes the design and the performance of the timing detector developed by the TOTEM Collaboration for the Roman Pots (RPs) to measure the Time-Of-Flight (TOF) of the protons produced in central diffractive interactions at the LHC. The measurement of the TOF of the protons allows the determination of the longitudinal position of the proton interaction vertex and its association with one of the vertices reconstructed by the CMS detectors. The TOF detector is based on single crystal Chemical Vapor Deposition (scCVD) diamond plates and is designed to measure the protons TOF with about 50 ps time precision. This upgrade to the TOTEM apparatus will be used in the LHC run 2 and will tag the central diffractive events up to an interaction pileup of about 1. A dedicated fast and low noise electronics for the signal amplification has been developed. The digitization of the diamond signal is performed by sampling the waveform. After introducing the physics studies that will most profit from the addition of these new detectors, we discuss in detail the optimization and the performance of the first TOF detector installed in the LHC in November 2015.

Screen printed antennas on textile substrate

This article deals with screen printed antennas on textile substrate that are used for data transmission between intelligent fireman suits. Today the smart textiles are developed in the whole world and research works are focused on integration of electronic devices and systems into textiles. There are different technologies how to do it. Screen printed electronic devices on textile substrates are one of the perspective possibilities how to create electronic devices on textiles. Screen printing technology uses conductive pastes for functional pattern creation. This technology reduces significantly the manufacturing cost, is simple to use and is more and more used in electronics.

arXiv : Test of UFSD Silicon Detectors for the TOTEM Upgrade Project

This paper describes the performance of a prototype timing detector, based on 50 μm thick Ultra Fast Silicon Detector, as measured in a beam test using a 180GeV/c momentum pion beam. The dependence of the time precision on the pixel capacitance and bias voltage is investigated in this paper. A timing precision from 30 ps to 100 ps (RMS), depending on the pixel capacitance, has been measured at a bias voltage of 180 V.

Timing performance of a double layer diamond detector

In order to improve the time precision of detectors based on diamonds sensors we have built a detector with two scCVD layers connected in parallel to the same amplifier. This work describes the design and the first measurements of such a prototype performed on a particle beam at CERN. With this different configuration we have obtained an improvement larger than a factor of 1.6–1.7 for the timing precision of the measurement when compared to a one layer scCVD diamond detector.

High performance polyphase FIR filter structures in VHDL language for Software Defined Radio based on FPGA

Digital filters are necessary in digital transmitter / receiver side and popularity of Software Defined Radio (SDR) is forcing complex digital signal processing blocks to be implemented in parallel design flow on FPGA or ASIC. The goal of this paper is to develop efficient pipelined polyphase FIR filter structures in VHDL language for RTL synthesis on FPGA. The proposed structures contain fully parallel polyphase decimation and interpolation FIR filter models. The first part of this paper is focused on formulation of distributed arithmetic technique with polyphase decomposition, which represents the core of designed models. The second part describes mentioned polyphase FIR VHDL models. The extensive emphasis will be put on efficient pipelined implementation with excellent registered performance and optimal design size balance. The third part of this paper deals with rapid design and simulation of proposed VHDL models. The result of RTL synthesis is finally discussed. Very good performance and optimal design size are main benefits of proposed polyphase FIR filters. Developed structures are very suitable for multichannel operation in digital I/Q receiver.

Autonomous and semi-autonomous radio commanding of VZLUSAT-1 nanosatellite from ground control station in Pilsen

Nano- and pico-satellites are currently used as low cost in-orbit-demonstrators of new technologies or for the university research. These satellites are launched to the low Earth orbits and radio commanded from the ground control stations. Most of them are equipped with narrow band transceivers working in UHF radio amateur frequency band, reaching only low data transmission rates. Low Earth orbits also limits the number and duration of satellite passing in the range of ground control station. One ground control station has approximately six satellite passes per day, each with duration only in few minutes. This strictly limits the amount of transmitted data between satellite and ground control station. In this paper the software controlled and assisted radio commanding of VZLUSAT-1 nanosatellite during the QB50 scientific mission is described. Two basic modes of satellite radio commanding are described with the aim to increase data throughput during commanding. Software controlled autonomous and software assisted semi-autonomous modes allow effective commanding of satellite while keeping the attention of satellite operator to the satellite condition and keeping the full control over the radio transmission as radio amateur regulation requires. Also the critical operational limits of satellite electronics faces to cosmic vacuum and radiation environment have to be continuously monitored for safety satellite operation.

Efficient VHDL implementation of symbol synchronization for software radio based on FPGA

The increasing popularity of Software Defined Radio is forcing complex digital signal processing blocks to be implemented in parallel design flow on FPGA or ASIC. One of the main sections of digital receiver is symbol synchronization block. The goal of this paper is to develop efficient Non-Data-Aided (NDA) feedback PLL-based synchronization scheme in VHDL language for RTL synthesis on FPGA. The first part of this paper is focused on formulation Maximum Likelihood (ML) criterion for timing error detector. This approach forms basic assumptions for derivation of the other timing error detectors like Zero-Crossing detector. The extensive emphasis will be put on simulation of synchronization models. This model is composed of interpolating filter, error timing detector and interpolation control block. The second part of this paper deals with simulation of proposed fully pipelined VHDL model and the results of RTL synthesis are discussed.

The signal splitter for laboratory GNSS signal distribution

The paper presents a design of a four way signal splitter working in L frequency band, for standard GNSS (Global Navigation Satellite Systems) signals. These splitters are used when more than one receiver has to be connected to one signal source, like an antenna, a signal distribution socket or a test signal generator. The advantage of the solution is realization by a PCB structure, without need of any expensive or hard to find special components. The splitter is also integrated with a transformation from 75 Ω to 50 Ω. Then cheaper 75 Ω cable can be used for the signal distribution system. Final results from the splitter testing are also included in the paper.

High efficient carrier phase synchronization for SDR using CORDIC implemented on an FPGA

This paper is devoted to the proposal of a highly efficient carrier phase synchronization subsystem for Software Defined Receiver. The proposed feedback phase-locked loop carrier synchronizer is suitable for parallel implementation on an FPGA for QPSK with the possibility of extension for m-QAM modulation. Direct Digital Synthesizer uses CORDIC algorithm in rotation mode for calculation of the sine and cosine of an angle. The angle of rotation is the uncompensated carrier phase offset. The carrier phase offset is derived by the closed-loop path created by phase error detector, PLL loop filter and accumulator control block. The paper will extensively focus on simulation of the proposed synchronization system. On the basis of this simulation, a complete, fully pipelined VHDL description model is created. Finally, RTL synthesis on an Altera Cyclone IV FPGA is presented.