Richard P. Kleihorst

XETAL-II: A 107 GOPS, 600mW Massively-Parallel Processor for Video Scene Analysis

Xetal-II is a SIMD processor with 320 processing elements delivering a peak performance of 107 GOPS on 16b data while dissipating 600mW. A 10Mb on-chip memory can store up to 4 VGA frames allowing efficient implementation of frame-iterative algorithms. A massively parallel interconnect provides an internal bandwidth of more than 1.3Tb/s to sustain the peak-performance. The 74mm2 IC is fabricated in 90nm CMOS.

Camera Mote with a High-Performance Parallel Processor for Real-Time Frame-Based Video Processing

This paper describes a new smart camera mote with a high performance SIMD (single-instruction multiple-data) processor. Previous versions of our camera mote were equipped with IC3D, a line-based processor. The mote described in this paper is equipped with Xetal-II, a processor designed for frame-based real-time video analysis. The processor uses 320 processing elements in parallel to achieve performance figures of more than 100GOPS with a power consumption of 600 mWatt at peak performance. The IC has a 10Mbit internal memory cache to store and work on 4 VGA frames. The internal bandwidth to this memory is more than 1.5 Tbit/s allowing multiple passes over the images within frametime. Augmented with hardware tools for object processing, the new mote opens the door for embedded active vision applications and other iterative techniques such as watershedding and distance transforms in collaborative camera networks.

Xetal: a low-power high-performance smart camera processor

Xetal is a digital signal processor to be combined with a 30 frames per second VGA-format CMOS or CCD image sensor or any other source of digital video data. The processor is fully programmable and therefore able to run a variety of algorithms ranging from image communication to machine vision. Xetal comprises a parallel processor array and a special purpose controller to achieve high computational performances (up to 5 GOPS) with a very modest power consumption. This can go down to 30 mW for simple applications such as a digital camera for video conferencing. The Xetal chip has been realized in a 0.18 /spl mu/m CMOS process and takes up an area of 25 mm/sup 2/.

Xetal-II: A 107 GOPS, 600 mW Massively Parallel Processor for Video Scene Analysis

Xetal-II is a single-instruction multiple-data (SIMD) processor with 320 processing elements. It delivers a peak performance of 107 GOPS on 16-bit data while dissipating 600 mW. A 10 Mbit on-chip memory is provided which can store up to four VGA frames, allowing efficient implementation of frame-iterative algorithms. A massively parallel interconnect provides an internal bandwidth of more than 1.3 Tbit/s to sustain the peak performance. The IC is realized in 90 nm CMOS and takes up 74 mm2.

Real-Time Human Posture Reconstruction in Wireless Smart Camera Networks

While providing a variety of intriguing application opportunities, a vision sensor network poses three key challenges. High computation capacity is required for early vision functions to enable real-time performance. Wireless links limit image transmission in the network due to both bandwidth and energy concerns. Last but not least, there is a lack of established vision-based fusion mechanisms when a network of cameras is available. In this paper a distributed vision processing implementation of human pose interpretation on a wireless smart camera network is presented. The motivation for employing distributed processing is to both achieve real-time vision and provide scalability for developing more complex vision algorithms. The distributed processing operation includes two levels. One is that each smart camera processes its local vision data, achieving spatial parallelism. The other is that different functionalities of the whole line of vision processing are assigned to early vision and object-level processors, achieving functional parallelism based on the processor capabilities. Aiming for low power consumption and high image processing performance, the wireless smart camera is based on an SIMD (single-instruction multiple-data) video analysis processor, an 8051 micro-controller as the local host, and wireless communication through the IEEE 802.15.4 standard. The vision algorithm implements 3D human pose reconstruction. From the live image data from the sensor the smart camera acquires critical joints of the subject in the scene through local processing. The results obtained by multiple smart cameras are then transmitted through the wireless channel to a central PC where the 3D pose is recovered and demonstrated in a virtual reality gaming application. The system operates in real time with a 30 frames/sec rate.

Architecture and Applications of wireless Smart Cameras (Networks)

A network of (wireless smart) cameras can analyse the scene from different views. Wireless smart cameras challenge the hardware for low-power consumption and high imaging performance. In this paper we introduce a wireless smart camera based on an SIMD video-analysis processor and an 8051 microcontroller as a local host. Wireless communication is through the IEEE 802.15.4 standard. The camera constructed in this paper is to enable application research into distributed smart camera systems.

Demo: Mouse sensor networks, the smart camera

This paper describes an extremely low-cost smart camera with imaging sensor, freely programmable DSP, power control and wired/wireless networking capabilities. The power consumption reaches from 3mW to 240mW depending on load and transmission rates and the BOM for a single device is now 25 euros. We were able to reduce both the power consumption and price by going to minimal resolution imagers (30×30 pixels) allowing us to reduce the performance demands on the DSP engine. The lower resolution, although with processing frame rates of up to 80fps, still allows many common applications for visual sensors such as object detection, fall detection, motion estimation and face detection. In addition, the resolution is low enough to guarantee privacy.

I.McIC: a single-chip MPEG-2 video encoder for storage

MPEG2 encoding is done mainly by distributors and publishers using professional equipment too expensive for the consumer market. I.McIC is a video encoder for this market, in particular for storage applications where higher bit rates can he tolerated (5-15 Mb/s) compared with bit rates for transmission (1.5-8 Mb/s). I.McIC operates in MPEG ML@SP mode and offers good video quality at 5 Mb/s and excellent quality at 10 Mb/s. For consumer storage applications, the video signals to be encoded might not be as clean as typical studio standards. Therefore, noise reduction is an integral part of I.McIC. I.McIC can share 16 Mb DRAM with an MPEG2 video decoder, organized as 4 times 4 Mb devices with 60 ns access. It can handle both 50 Hz and 60 Hz video sources. To interface to a video source, I.McIC uses a line-locked clock generated by the A/D converter and running at 27 MHz.

Low-complexity scalable image compression

We have developed a scalable image compression scheme with a good performance-complexity trade-off. Like JPEG, it is based on the 8/spl times/8 block discrete cosine transform (DCT), but it uses no additional quantization or entropy coding (such as Huffman or arithmetic coding). Bit-rate or quality scalability is enabled by encoding the DCT coefficients bit plane by bit plane, starting at the most significant plane. The individual bit planes are efficiently encoded using simple rectangular zones. Our method offers about the same compression performance as JPEG, but at a significant lower complexity and with the additional feature of scaling the bit rate by simply truncating the generated bit string.

Coding scheme for low energy consumption fault-tolerant bus

We address the problem of devising the error correcting code which, if used to encode the information on a very deep submicron (VDSM) bus, allows us to achieve fault-tolerance with the minimal impact on bus power consumption and power-delay product. In particular, we first report the results of an analysis that we performed on power dissipation in VDSM fault-tolerant busses using Hamming single error correcting codes. We show that no power saving is possible by choosing between different optimal Hamming codes with the same redundancy. We then propose a new coding scheme which provides a reduction of the energy consumption and power-delay product of over the 11.5% and 45%, respectively, with respect to the optimal (7,4) Hamming code, for a 0.13/spl mu/m CMOS technology bus.