Ricky A. Jackson

Transition from precise to accurate critical dimension metrology

A new measurement system analysis (MSA) methodology has been developed at Texas Instruments (TI) to evaluate the status of the 65 nm technology critical dimension (CD) metrology and its readiness for production. Elements of the methodology were used in a previously reported scatterometry evaluation [1]. At every critical process level the precision, bias, linearity and total measurement uncertainty (TMU) were evaluated for metrology fleet over extended periods of time, and with the technology representative set of samples. The samples with variations that fully covered and often exceeded process space were pre-calibrated by CD atomic force microscope (AFM). CD AFM measurement precision was determined for every analyzed process level based on repeated measurements conducted over several days. The National Institute of Standards and Technologies (NIST) traceable standards were used to verify CD AFM line CD and scale calibrations. Therefore, for the first time the NIST traceability has been established for CD metrology at every critical process level for the entire technology. The data indicates an overall healthy status of the 65 nm CD metrology. Sub-nanometer accuracy has been established for gate CD metrology. The thorough CD metrology characterization and specifically absolute CD calibration were instrumental in seamless technology transfer from 200 mm to 300 mm fabs. The qualification of CD metrology also revealed several problems. Most of these are well-known from previous studies and should soon be addressed. CD scanning electron microscopy (SEM) has a systematic problem with bias of CD measurements. The problem is common for several front-end and back-end of line process levels. For most process levels, TMU of CD SEM is noticeably affected by sample modification inflicted by electron irradiation (shrinkage, charging, buildups, etc.). This causes problems, especially in the case of fleet TMU evaluation. An improved data collection methodology should be devised to minimize the impact of sample modification on fleet TMU measurements. The reported progress in semiconductor industrial CD metrology became possible after a recent breakthrough in line CD standard technology [2,3], recognition of CD AFM as an instrument for CD traceability [4,5] and development of the concept and mathematical tools for TMU analysis [6,7].

Fabrication and Performance of Integrated Fluxgate for Current Sensing Applications

The recently developed Fluxgate technology from Texas Instruments has enabled the production of the industry’s first current sensing integrated circuit with a fully integrated fluxgate device and a compensation coil driver. This paper presents an overview of the Fluxgate technology, focusing on the fabrication and performance of the integrated magnetic field sensing device.

Characterization of bending CD errors induced by resist trimming in 65 nm node and beyond

Resist trimming is a technique that is often used to close the gap between line widths which can be repeatedly printed with currently available lithography tools and the desired transistor gate length. For the 65-nm node, the resist line width delivered at pattern is between 60 to 70 nm while the final transistor gate length is usually targeted between 35 to 45 nm. The 15 to 35 nm critical dimension (CD) difference can be bridged by resist trimming. Due to the stringent gate CD budget, a resist trimming process should ideally have the following characteristics: i) no degradation in CD uniformity; ii) no damage in pattern fidelity; iii) controllable CD trim rate with good linearity; and iv) no degradation in line edge roughness (LER) or line width roughness (LWR). Unfortunately, a realistic resist trimming process is never perfect. In particular, resist consumption and the resultant internal stress build-up during resist trimming can lead to resist line bending. The effect of bent resist lines is a higher post-etch CD and significantly degraded local CD uniformity (LCDU). In order to reduce resist bending CD errors (defined as the difference between the post-etch CD and the design CD due to resist bending after trimming) several useful procedures either in layout or in processes are presented. These procedures include: i) symmetrically aligning gates to contact pads and field connecting poly in the circuit layout; ii) enlarging the distance between contact pad (or field connecting poly) to active area within the limits of the design rules (DR) and silicon real estate; iii) adding assist features to the layout within the DR limits; iv) minimizing resist thickness; and v) applying special plasma cure before resist trim.

Characterizing a surface imaging process in a high-volume DRAM manufacturing production line

The manufacturing of the next generation of DRAMs will require microlithographic capability in the 0.5 micrometers range. Our goal is to develop this capability using g-line optical microlithography; and i- line when g-line fails. To determine if surface-imaging is a viable alternative to extend the practical resolution limit of g-line lithography in a manufacturing environment, we have set up and characterized DESIRE, a surface-imaging process, in a high-volume DRAM manufacturing production line. This characterization study includes: (a) determination of basic lithographic data, (b) measurement of linewidth as the criterion to determine the stability of the process over time, (c) pattern transfer and stability of the resist to dry-etch processes, (d) measurement of any radiation-induced damage taking place during dry- development.

Using Pattern Quality confirmation to control a metal-level DUV process with a top-down CD-SEM

As critical-feature patterning processes increase in complexity and sensitivity, conventional critical dimension (CD) measurements may not afford the level of process control required for effective device production. By comparing recorded top-down scanning-electron-microscope (SEM) images to a predefined reference image, Pattern Quality Confirmation (pQC) enables a more detailed analysis of measurements captured by KLA-Tencor 8XXX series scanning-electron microscopes. An example of the utility of this additional information is discussed below for a metal interconnect level patterned with a conventional deep-ultraviolet (DUV) photolithography process. In particular, we demonstrate that for certain ranges of focus-exposure conditions, conventional post-develop CD measurements remain well within specification, however, when etched, the resulting metal-line CDs are significantly below the lower specification limit. The pQC image analysis results, however, predict the observed post-etch CD variations, and consequently offer sensitivity to yield-limiting focus drifts and excursions, enabling effective product-dispositioning (rework) decisions.

Integrating diffusion enhanced silylated resist into a single‐layer resist dynamic random access memory production line

The manufacturing of the next generation of dynamic random access memory (DRAM) will require lithographic capability in the 0.5 μm range. Not surprisingly, their requirements push the limits of optical microlithography, thereby rapidly diminishing the process window. This problem becomes more acute at the end of the line where topography and reflectivity have the largest impact on an already strained processing budget. Surface imaging [G. Taylor and T. Wolf, J. Electrochem. Soc. 127, 2665 (1980)] is less sensitive to topography and reflectivity than conventional lithography. Thus, integrating a surface imaging process into a conventional single‐resist processing line is an attractive option to extend the practical resolution limit of current optical lithography without resorting to more complex multilayer resist schemes or more expensive imaging tools. The diffusion enhanced silylated resist process is the most mature of the surface imaging processes commercially available today. This report addresses int...

Stepper Lens Characterization Using A Field Emission SEM

A method of stepper lens evaluation has been developed which utilizes a simple resolution test pattern of the type usually supplied with the stepper. Measurements are made using an automated field emission SEM equipped to perform whole wafer non-destructive critical dimension analysis. Measurement data on focus and sizing is then analyzed by a computer program easily run on a small personal computer. Information on reticle sizing errors and wafer flatness may also be included in the analysis to minimize errors.