Ridha Djemal

Three-Class EEG-Based Motor Imagery Classification Using Phase-Space Reconstruction Technique

Over the last few decades, brain signals have been significantly exploited for brain-computer interface (BCI) applications. In this paper, we study the extraction of features using event-related desynchronization/synchronization techniques to improve the classification accuracy for three-class motor imagery (MI) BCI. The classification approach is based on combining the features of the phase and amplitude of the brain signals using fast Fourier transform (FFT) and autoregressive (AR) modeling of the reconstructed phase space as well as the modification of the BCI parameters (trial length, trial frequency band, classification method). We report interesting results compared with those present in the literature by utilizing sequential forward floating selection (SFFS) and a multi-class linear discriminant analysis (LDA), our findings showed superior classification results, a classification accuracy of 86.06% and 93% for two BCI competition datasets, with respect to results from previous studies.

A real-time FPGA-based implementation of target detection technique in non homogenous environment

This paper presents a high speed real-time target detection system for non homogenous environment based on FPGA Technology. The system implements a Backward Automatic Censored Ordered Statistics Detector (B-ACOSD) to maintain a Constant False Alarm Rate (CFAR) for Radar system with a time constraints in term of signal computing and target identification. The design flow and the hardware implementation of each module are introduced in detail. The proposed system can operate up to 115 MHz by using full pipeline organization and parallel computing which increase the speed up of the target detection system to satisfy the real-time constraints. The proposed architecture is designed, implemented, and tested using Stratix II EP2S60F672C3N FPGA Board. The system has the advantages of being simple, fast, and flexible with low development cost for a reference window of length 16 cells.

Efficient hardware architecture of 2D-scan-based wavelet watermarking for image and video

This paper describes an efficient hardware architecture of 2D-Scan-based-Wavelet watermarking for image and video. The potential application for this architecture includes broadcast monitoring of video sequences for High Definition Television (HDTV) and DVD protection and access control. The proposed 2D design allows even distribution of the processing load onto a set of filters, with each set performing the calculation for one dimension according to the scan-based process. The video protection is achieved by the insertion of watermarks bank within the middle frequency of wavelet coefficients related to video frames by their selective quantization. The 2-D DWT is applied for both video stream and watermark in order to make the watermarking scheme robust and perceptually invisible. The proposed architecture has a very simple control part, since the data are operated in a row-column-slice fashion. This organization reduces the requirement of on-chip memory. In addition, the control unit selects which coefficient to pass to the low-pass and high-pass filters. The on-chip memory will be small as compared to the input size since it depends solely on the filter sizes. Due to the pipelining, all filters are utilized for 100% of the time except during the start-up and wind-down times. The major contribution of this research is towards the selection of appropriate real time watermarking scheme and performing a trade-off between the algorithmic aspects of our proposed watermarking scheme and the hardware implementation technique. The hardware architecture is designed, as a watermarking based IP core with the Avalon interface related to NIOS embedded processor, and tested in order to evaluate the performance of our proposed watermarking algorithm. This architecture has been implemented on the Altera Stratix-II Field Programmable Gate Array (FPGA) prototyping board. Experimental results are presented to demonstrate the capability of the proposed watermarking system for real time applications and its robustness against malicious attacks.

High performance Architecture of Integrated Protocols for Encoded Video Application

Despite the evolution of high-speed communication network to accommodate an increasingly number of applications with diverse service requirements, there still exist a number of barriers related to the deployment of the encoded video over the ATM network. In fact, additional works have to be devoted to improve protocol architecture and to guarantee the QoS. In this paper, we first analyze the main parameters affecting the visual quality of real video pictures. Then, we define specific services to be implemented at the network interface level. We also discuss the proposed integrated protocols architecture for real time application such as video coding illustrating the function to support the challenges of managing real time services over high speed network. In fact, data cells are exposed to delays and losses, which affect the quality of the video signal. Therefore, we have to perform the adequate processing in order to keep the quality of service on an acceptable level. In this article, we propose the design of an interface between the MPEG-2 standard and the ATM network in order to improve the video visual quality. Our approach tries to overcome the difficulty imposed by traditional random cell discarding due to the bursty aspect of the traffic and the variable bit rate (VBR) transmission, nature of compressed video. The performance evaluation shows the effectiveness of the proposed interface architecture with the set of mechanisms in improving the robustness of the video delivery system.

An adaptive EEG filtering approach to maximize the classification accuracy in motor imagery

We propose in this paper a novel approach of adaptive filtering of EEG signals. The filter adapts to the intrinsic characteristics of each person. The goal of the proposed method is to enhance the accuracy of the home devices system controlled by the thoughts related to two motor imagery actions. μ-rhythm and β-rhythm are the specific returned bands that contain the information. The main idea of the proposed method is to preserve the frequency bands of interest with a different value of the SNR on the stop-band. Our experimental results show the benefits of a suitable tuning of the filter on the accuracy of the classifier on the output of the EEG system. The proposed approach outperforms significantly performances reported in the literature and the effectively enhancement of the classification accuracy can reach up to 40% based only on filtering tuning.

A DWT-entropy-ANN based architecture for epilepsy diagnosis using EEG signals

Electroencephalogram (EEG) is one the most common tools for epilepsy diagnosis and analysis. Currently, epilepsy diagnosis is still mainly performed by a neurologist through manual or visual inspection of EEG signals. In this article, we develop a computer aided diagnosis (CAD) for epilepsy based on discrete wavelet transform (DWT), Shannon entropy and feed-forward neural network (FFNN). DWT decompose EEG signals into several frequency sub-bands such as delta, theta, alpha, beta and gamma. Shannon entropy extract the EEG features from each these frequency sub-bands. Finally, FFNN classifies the corresponding EEG signals into “normal” or “epileptic” class based on the extracted features. Our experimental results using publicly available University of Bonn EEG dataset show perfect accuracy (100%).

An embedded implementation of home devices control system based on brain computer interface

This paper presents a new embedded architecture for home devices control system directed through motor imagery actions captured by EEG headset. The proposed system is validated by an offline approach which consists on using available public data-set. These recording are always accompanied with noise and useless information related to the equipment, eyes blinking and many others resources of artifacts. For this reason, a complex EEG signal processing is required; starting by filtering EEG to keep the frequency of interest which is located on μ-rhytm and β-rhytm bands in our case; followed by the extraction of useful feature to minimize the size of EEG data and enhance the probability of classifying each trial correctly. A prototype of our proposed embedded system has been implemented on Stratix IV FPGA Board. The prototype operates at 200 MHz and performs real-time classification with an execution delay of 0.5 second per trial and an accuracy average of 72%.

A novel formal verification approach for RTL hardware IP cores

We present a promising formal verification methodology based on the inductive approach using the imPROVE-HDL tool. This methodology is dedicated for RTL IPs or IP-based digital/logic hardware designs to prove the correctness of their temporal properties related to the control-dominated architecture model. Each temporal property can be checked through the IP interface where all properties have to be proved or disproved. We developed a new methodology to generate the appropriate environment of the IP interface according to the design context (master, slave, arbiter and decoder) before starting the verification of all properties one by one. When all temporal properties are verified, we generate some test sequences that contain a complex scenario to check the compatibility between all properties. We implemented our methodology to generate the appropriate environment and applied the inductive approach to verify various properties of two real IP designs using the imPROVE-HDL tool developed by TNI-Valiosys. The first design is an RTL IP-based digital hardware dedicated for real time video processing, where the second one performs an AHB to AHB Bridge. On these designs, we successfully proved few properties and discovered a design violation.

A flow control approach for encoded video applications over ATM network

This paper addresses the problem of transmission of digital video communication over B-ISDN such as the ATM network. It provides the appropriate solution based on a good knowledge of both the video system interface design and broadband network capabilities. An interface between MPEG-2 and ATM network architecture is studied to improve the video visual quality. The presented approach try to overcome the difficulty imposed by traditional random cell discarding due to the bursty and variable bit rate transmission, nature of compressed video. The presented approach is guided by using a dynamic bandwidth management with the maximum flexibility via an appropriate scheduling algorithm and a new cell discarding scheme. In order to support these mechanisms, enhancement to the ATM adaptation layer is performed and a new MPEG-2 mapping strategy is also proposed. The performance evaluation have shown a significant minimization of losses ATM cells and a best video quality compared with the sequence transmitted without flow control.

A Hardware/Software Prototype of EEG-based BCI System for Home Device Control

This paper presents a design exploration of a new EEG-based embedded system for home devices control. Two main issues are addressed in this work: the first one consists of an adaptive filter design to increase the classification accuracy for motor imagery. The second issue deals with the design of an efficient hardware/software embedded architeclture integrating the entire EEG signal processing chain. In this embedded system organization, the pre-processing techniques, which are time consuming, are integrated as hardware accelerators. The remaining blocks (Intellectual Properties - IP) are developed as embedded-software running on an embedded soft-core processor. The pre-processing step is designed to be self-adjusted according to the intrinsic characteristics of each subject. The feature extraction process uses the Common Spatial Pattern (CSP) as a filter due to its effectiveness to extract the ERD/ERS (Event-Related Desynchronization/ Synchronization) effect, where the classifier is based on the Mahalanobis distance. The advantage of the proposed system lies in its simplicity and short processing time while maintaining a high performance in term of classification accuracy. A prototype of the embedded system has been implemented on an Altera FPGA-based platform (Stratix-IV). It is shown that the proposed architecture can effectively extract discriminative features for motor imagery with a maximum frequency of 150 MHz. The proposed system was validated on EEG data of twelve subjects from the BCI competition data sets. The prototype performs a fast classification within time delay of 0.399 second per trial, an accuracy average of 94.47 %, an average transfer rate over all subjects of 20.74 bits/min. The estimated power consumption of the proposed system is around 1.067 Watt (based on an integrated tool-power analysis of Altera corporation).