Rikido Yonezawa

Error in propagation velocity due to staircase approximation of an inclined thin wire in FDTD surge Simulation

This paper presents the result of a study on the error in propagation velocity introduced by the staircase approximation of a thin wire in the finite difference time domain (FDTD) surge simulation. The FDTD method directly solves Maxwells equations by discretizing the space of interest into cubic cells. Thus, it is suitable for solving very-fast surge phenomena which cannot be dealt with by conventional techniques based on the lumped- and distributed-parameter circuit theories. However, FDTD has a limitation that the shape of a conductive object must be modeled by a combination of sides of cells with forced zero electric fields. This indicates that a thin wire, one of the most important components in the surge simulation, results in a staircase approximation, if the wire is not parallel to any of the coordinate axes used for the discretization. A staircase approximation gives a slower propagation velocity due to the zigzag path which is longer than the actual length of the wire. For precise simulations, the error in propagation velocity has to be clarified quantitatively. In this paper, extensive simulations are carried out to obtain the velocity versus inclination characteristic, and it is deduced that the maximum error in propagation velocity is less than 14%.

Error in propagation velocity due to staircase approximation of an inclined thin wire in FDTD surge simulation

Summary form only given. This paper presents the result of a study on the error in propagation velocity introduced by the staircase approximation of a thin wire in the FDTD surge simulation. The FDTD method directly solves Maxwells equations by discretizing the space of interest into cubic cells. Thus, it is suitable for solving very-fast surge phenomena, which cannot be dealt with by conventional techniques based on the circuit theories. However, FDTD has a limitation that the shape of a conductive object must be modeled by a combination of sides of cells with forced zero electric fields. This indicates that a thin wire, one of the most important components in the surge simulation, results in a staircase approximation, if it is not parallel to any of the coordinate axes used for the discretization. A staircase approximation gives a slower propagation velocity due to the zigzag path, which is longer than the actual length of the wire. For precise simulations, the error in propagation velocity has to be clarified quantitatively. In this paper, extensive simulations are carried out to obtain the velocity versus inclination characteristic, and it is deduced that the maximum error in propagation velocity is less than 14 %.

Application of a Varying Elements Tracing Method to Partial Refactorization in an Electromagnetic Transient Analysis Program

Faster calculation methods are desired for electromagnetic transient (EMT) simulation programs, since circuits simulated are becoming increasingly larger and more complex. If there are time-varying and non-linear elements in the circuit to be solved, the solution process requires repeated factorization of the coefficient matrix of the circuit equations. The repeated factorization, which is often called refactorization, significantly increases the computation time. Up to now, the bottom right arranging (BRA) method has been applied for refactorization in EMT simulation programs in order to reduce the computation load. In this paper, the author proposes the use of the varying elements tracing (VET) method, which is one of the refactorization methods proposed for power flow calculations, for an offline EMT simulation program. Using some test circuits, the computation time by the BRA method and that by the VET method are examined, and the following facts are found. In most test circuits, both methods greatly improve refactorization speed, but in some test circuits, the BRA method shows degraded refactorization speed due to increased fill-ins. As for the entire EMT simulation time, the VET method improves the refactorization speed by a factor of 1.6 times at most. On the other hand, the BRA method improves the refactorization speed by a factor of 1.5 times in the best case but degrades it in some test circuits.