Rinse Wester

A two step hardware design method using CλaSH

In order to effectively utilize the growing number of resources available on FPGAs, higher level abstraction mechanisms are needed to deal with increasing complexity resulting from large designs. Functional hardware description languages, like the CλaSH HDL, offer adequate abstraction mechanisms such as polymorphism and higher-order functions. This paper describes a two step design method to implement a DSP application on an FPGA, starting from a mathematical specification, followed by an implementation in CλaSH. A non trivial application, a particle filter, is used to evaluate both the method and CλaSH. First, a straightforward translation is performed from the mathematical definition of a particle filtering to Haskell, a functional programming language with syntax and semantics similar to CλaSH. Secondly, minor changes are applied to the Haskell implementation so that it is accepted by the CλaSH compiler. The resulting hardware produced by our method is evaluated and shows that this method eases reasoning about structure and parallelism in both the mathematical definition and the resulting hardware.

Low-cost multi-channel underwater acoustic signal processing testbed

Current systems for multi-channel underwater signal processing suffer from a tied relation between the hardware and physical layer software or require a large amount of engineering work. To provide a low-cost, small form factor and flexible solution, this work presents a multi-channel testbed consisting of an off-the-shelf FPGA board and a simple expansion board. Nonetheless, the proposed testbed provides the flexibility and processing power to evaluate novel multi-channel physical layer algorithms.

Designing a dataflow processor using CλaSH

In this paper we show how a simple dataflow processor can be fully implemented using CλaSH, a high level HDL based on the functional programming language Haskell. The processor was described using Haskell, the CλaSH compiler was then used to translate the design into a fully synthesisable VHDL code. The VHDL code was synthesised with 90 nm TSMC libraries and placed and routed. Simulation of the final netlist showed correct behaviour. We conclude that Haskell and CλaSH are well-suited to define hardware on a very high level of abstraction which is close to the mathematical description of the desired architecture. By using CλaSH, the designer does not have to care about internal implementation details like when designing with VHDL. The complete processor was described in 300 lines of code, some snippets are shown as illustration.

Design-time improvement using a functional approach to specify GraphSLAM with deterministic performance on an FPGA

SLAM is a fundamental problem in robotics that can be solved by a set of algorithms that are known to have large computational complexity. GraphSLAM contains a rapidly growing system of equations which are often solved by sparse evaluation techniques. This paper proposes a technique to evaluate sparse equations on an FPGA by restricting the maximum amount of items in the system. The implementation is done using CλaSH which allows a transformation from mathematical descriptions to a hardware design. The results show a scalable hardware design that can be used to solve small and large systems with dynamic parallelism.

A space/time tradeoff methodology using higher-order functions

Large digital signal processing applications like particle filtering require a tradeoff between execution time and area in order to scale on FPGAs. This research focuses on developing a methodology to make this tradeoff based on structure in the mathematical description of the application. Structure is expressed using higher-order functions which are transformed using tradeoff rules to reduce area usage on FPGA.