Rizwan Bashirullah

An optimal design methodology for inductive power link with class-E amplifier

This paper presents a design methodology of a highly efficient power link based on Class-E driven, inductively coupled coil pair. An optimal power link design for retinal prosthesis and/or other implants must take into consideration the allowable safety limits of magnetic fields, which in turn govern the inductances of the primary and secondary coils. In retinal prosthesis, the optimal coil inductances have to deal with the constraints of the coil sizes, the tradeoffs between the losses, H-field limitation and dc supply voltage required by the Class-E driver. Our design procedure starts with the formation of equivalent circuits, followed by the analysis of the loss of the rectifier and coils and the H-field for induced voltage and current. Both linear and nonlinear models for the analysis are presented. Based on the procedure, an experimental power link is implemented with an overall efficiency of 67% at the optimal distance of 7 mm between the coils. In addition to the coil design methodology, we are also presenting a closed-loop control of Class-E amplifier for any duty cycle and any value of the systemQ.

A Wireless Power Interface for Rechargeable Battery Operated Medical Implants

This brief presents a highly integrated wirelessly powered battery charging circuit for miniature lithium (Li)-ion rechargeable batteries used in medical implant applications. An inductive link and integrated Schottky barrier rectifying diodes are used to extract the DC signal from a power carrier while providing low forward voltage drop for improved efficiency. The battery charger employs a new control loop that relaxes comparator resolution requirements, provides simultaneous operation of constant-current and constant-voltage loops, and eliminates the external current sense resistor from the charging path. The accuracy of the end-of-charge (EOC) detection is primarily determined by the voltage drop across matched resistors and current-sources and the offset voltage of the sense comparator. Experimental results in 0.6-mum 3M-2P CMOS technology indicate that plusmn1.3% (or plusmn20 muA) EOC accuracy can be obtained under worst case conditions for a comparator offset voltage of plusmn5 mV. The circuit measures roughly 1.74 mm2 and dissipates 8.4 mW in the charging phase while delivering a load current of 1.5 mA at 4.1 V (or 6.15 mW) for an efficiency of 73%.

A Delay-Locked Loop Synchronization Scheme for High-Frequency Multiphase Hysteretic DC-DC Converters

This paper reports a delay locked loop (DLL) based hysteretic controller for high-frequency multiphase buck DC-DC converters. The DLL control loop employs the switching frequency from a hysteretic comparator to automatically synchronize the remaining phases. A dedicated duty cycle control loop is used to enable current sharing and ripple cancellation. We demonstrate a 25-70 MHz 4-phase converter with fast hysteretic control and output conversion range of 17%-80% while achieving a peak efficiency of 83% and peak-to-peak ripple within 10% in standard 0.6 mum 5 V CMOS process.

A 90–240 MHz Hysteretic Controlled DC-DC Buck Converter With Digital Phase Locked Loop Synchronization

This paper reports a digital phase locked loop (D-PLL) based frequency locking technique for high frequency hysteretic controlled dc-dc buck converters. The proposed converter achieves constant operating frequency over a wide output voltage range, eliminating the dependence of switching frequency on duty cycle or voltage conversion range. The D-PLL is programmable over a wide range of parameters and can be synchronized to a clock reference to ensure proper frequency lock and switching operation outside undesirable power supply resonance bands. The stability and loop dynamics of the proposed converter is analyzed using an analog equivalent PLL behavioral model which describes the dc-dc converter as a voltage-controlled oscillator (VCO). We demonstrate a 90-240 MHz single phase converter with fast hysteretic control and output conversion range of 33%-80%. The converter achieves an efficiency of 80% at 180 MHz, a load response of 40 ns for a 120 mA current step and a peak-to-peak ripple less than 25 mV. The circuit was implemented in 130 nm digital CMOS process.

Technology and Signal Processing for Brain-Machine Interfaces

Neural interfaces hold the promise to become one of the great technological advancements of the 21st century because they can provide new means of communication by directly accessing and interpreting brain intentional states. This article presents a set of grand challenges for brain-machine interfaces (BMI) and investigates recent advances in neurotechnology and signal processing methods to overcome them.

A 16 Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling

This paper describes an adaptive bandwidth bus (ABB) architecture based on hybrid current/voltage mode repeaters for long global RC interconnect static busses that achieves high-data rates while minimizing the static power dissipation associated with current-mode signaling. Attaining a maximum aggregate bandwidth of 16 Gb/s (i.e., 1 Gb/s per line) across lossy on-chip interconnects spanning 1.75 cm in length, the bus core fabricated in 0.35 /spl mu/m CMOS technology dissipates approximately 93 mW with a supply of 2.5 V and signal activity of 0.5, equivalent to 5.71 pJ/bit. Experimental results using a 16-bit reference bus design that can be externally programmed to operate in voltage, current or adaptive modes indicate a 50% reduction in power dissipation over current-mode (CM) sensing, and an improvement in interconnection delay and signaling bandwidth of 35%-70% and 66% over voltage-mode (VM) sensing, respectively.

Florida Wireless Implantable Recording Electrodes (FWIRE) for Brain Machine Interfaces

This paper reviews on-going efforts towards the development of the Florida wireless implantable recording electrodes (FWIRE). The FWIRE microsystem platform is a fully implantable flexible substrate microelectrode array that employs state-of-the-art integrate-and-fire (IF) signal representation and wireless interface circuitry for recording neural activity from behaving rodents. The modular nature of the implantable neural recording electrode allows future enhancements to be seamlessly added to improve functionality including but not limited to rechargeability through inductive coupling, custom microelectrode arrays, higher capacity batteries, and more advanced integrated circuit technologies. This paper concentrates on custom integrated circuits such as neural interfacing amplifiers, baseband signal processing, wireless data and power interfaces, and battery management system.

A Low Power ASK Clock and Data Recovery Circuit for Wireless Implantable Electronics

This paper describes a low power clock and data recovery (CDR) circuit with integrated ASK demodulator for wireless implantable neural recording microsystems. A modulation scheme based on amplitude shift-keying (ASK) and pulse position modulation (PPM) is employed to simplify the complexity of implant circuits and reduce power transmission requirements. A charge-pump based CDR circuit is used to extract non-return to zero data from the demodulated waveforms. A prototype has been fabricated in 2-poly 3-metal 0.6mum bulk CMOS technology in order to validate circuit functionality. The receiver front-end exhibits a sensitivity of 3.2mV p-p at 1MHz. The ASK demodulator and CDR operates over an input data range of 4kbs to 18kbs, measures 300pm by 600pm and dissipates 70pW from a 2.7V supply

Airgap Interconnects: Modeling, Optimization, and Benchmarking for Backplane, PCB, and Interposer Applications

Frequency and time domain models are developed for backplane (BP), printed circuit board (PCB), and silicon interposer (SI) links using six-port transfer matrices (ABCD matrices) for bumps, vias and connectors, and coupled multiconductor transmission lines for traces. The six-port transfer matrix approach enables easy computation of the transfer function, as well as near-end and far-end crosstalk. The intersymbol interference is accounted for by computing the pulse response for the worst case bit pattern. Furthermore, the models developed here are used to optimize the data-rate and trace width for each of the links, so that the aggregate bandwidth obtained per joule of energy supplied to the link is maximized. The modeling and optimization approach developed here serves as a good platform to compare the air-gap interconnects against BP, PCB, and SI interconnects on lossy dielectrics. It is shown that air-gap interconnects can provide an aggregate bandwidth improvement of 3x-4x for BP links at a comparable energy per bit, and a 5x-9x improvement in aggregate bandwidth of PCB links at the expense of 20% higher energy per bit. For SI links, airgap interconnects are shown to provide a 2x-3x improvement in aggregate bandwidth and a 1x-1.5x improvement in energy per bit.

An asymmetric RF tagging IC for ingestible medication compliance capsules

This paper presents a feasibility study of a low power electronic RF tagging device and a printed capsule antenna for medication compliance monitoring. RF transponders attached directly to the outer surface of a standard sized capsule can potentially serve as a cost-effective method of validating medication compliance via electronic detection of an ingested pill inside the digestive tract. The electrical radiation characteristics of a small biocompatible antenna are analyzed inside a human body model for various FCC telemetry bands using the finite difference time domain (FDTD) method. Based on this study, a novel asymmetric RF tagging IC is reported. The device is powered by low frequency AC signals to create externally detectable RF bursts in the 915MHz ISM band. A test chip was fabricated in 130nm CMOS technology and experimentally validated inside a phantom solution that mimics the human torso.