Robert A. Kertis

A 12-ns ECL I/O 256 K*1-bit SRAM using a 1- mu m BiCMOS technology

An ECL (emitter-coupled-logic) I/O 256K*1-bit SRAM (static random-access memory) has been developed using a 1- mu m BiCMOS technology. The double-level-poly, double-level-metal process produces 0.8- mu m CMOS effective gate lengths and polysilicon emitter bipolar transistors. A zero-DC-power ECL-to-CMOS translation scheme has been implemented to interface the ECL periphery circuits to the CMOS decode and NMOS matrix. Low-impedance bit-line loads were used to minimize read access time. Minimization of bit-line recovery time after a write cycle is achieved through the use of a bipolar/CMOS write recovery method. Full-die simulations were performed using HSPICE on a CRAY-1. >