Robert Andrew Kertis

A 7 Mbyte/s (65 MHz), mixed-signal, magnetic recording channel DSP using partial response signaling with maximum likelihood detection

A mixed-signal, 6.0-MByte/s PRML (partial-response maximum-likelihood) read/write channel has been developed using analog circuits and 20K CMOS gates on a single chip. The 7.5-mm/sup 2/ chip uses a 5-V, 1-/spl mu/m, BiCMOS process with a 6-GHz NPN and a 1-GHz PNP and is packaged in a 100 lead metal QFPK. The overall chip architecture is discussed along with specific analog functions and their circuit techniques. This IC will allow production of a 2-GByte, 3.5-in, rigid disk drive with low error rates.

A 16 MB/s PRML read/write data channel

PRML data channels recently have become more prevalent in the industry. This paper describes an IC that contains all required analog and digital functions for a complete read channel, with the exception of the read-head pre-amplifier. This chip is believed to be the highest data rate channel in production at the time of this writing. This channel uses an 8/9 rate data encoder to constrain the data sequence written on the disk. These constraints make it possible to maintain gain and timing loop control as well as limit the length of path memory within the Viterbi detector. The write data is processed by a precompensation circuit that predistorts the data to ensure proper timing relationships during read back. Precompensation is in increments of 200ps steps with the availability of up to 15 steps.