Robert B. Garner

The scalable processor architecture (SPARC)

An introduction is given to the SPARC architecture and its more interesting features. The discussion covers the registers (both window and floating-point), and instructions, including formats, load/store, integer computation, control transfer, floating-point computation, and coprocessor. A brief comparison with Berkeley RISC (reduced-instruction-set-computer) and SOAR is provided.<<ETX>>

SPARC: a scalable processor architecture

Abstract SPARC defines a general purpose 32-bit scalable processor architecture. The simple yet efficient nature of the architecture allows cost effective and high-performance implementations across a range of technologies. Since its first implementation done in Fujitsus C20K gate array, a number of implementations have been announced in various technologies including bipolar ECL. All these designs implement the same instruction set. Thus an application program behaves identically and produces the same results on all SPARC platforms executing the operating systems that support the architecture.

SPARC: An ASIC Solution for High-Performance Microprocessors

Sun Microsystems’ Scalable Processor Architecture (SPARC) defines a general purpose 32-bit processor architecture. It was designed to allow cost effective and high performance implementations across a range of technologies. The simple yet efficient nature of the architecture makes it possible to implement it in a short period of time. It also makes SPARC very attractive for implementation in ASIC technologies, without sacrificing high performance. Its first implementation has been done in Fujitsu’s C20K gate array, and is the first high performance microprocessor to be designed in an ASIC technology. This paper summarizes the architecture and its gate array implementation.