Robert H. Bishop

Packet switch with configurable bandwidth allocation precision

Multiple path switch and switching algorithms

Pass gate decoder for a multiport memory dEvice that uses a single ported memory cell array structure

Priority encoding for FIFO memory devices that interface multiple ports to a data receiving device

Packet switch with configurable virtual channels

Asynchronous FIFO increment and decrement control for interfaces that operate at differing clock frequencies

Old virtual queues technique for routing data packets in a packet switch

Packet based switch with destination updating

Integrated circuit memory devices having control circuits therein that provide column redundancy capability

Device with modified round robin arbitration scheme and method for transferring data