Robert Illing

Non-linear thermal modeling of DMOS transistor and validation using electrical measurements and FEM simulations

The relevance of thermally non-linear silicon material models for transient thermal FEM simulations of smart power switches (SPS) is proved by a power silicon test device consisting of two power transistors and eleven integrated temperature sensors distributed over the silicon die. The test device is heated up by turning on an integrated power transistor in short-circuit for several milliseconds at two different initial temperatures. These thermal events correspond to a real situation that can occur in the application. The power dissipation in the power transistor is calculated from the measured source current and drain-source voltage, and subsequently used as an input to the FEM simulation. The temperature change on the test chip is measured by the integrated temperature sensors. An FEM model of the test chip encapsulated in a plastic package has been built in the FlexPDE simulator. The emphasis is put on the macroscopic modeling of the power transistor where an electro-thermal approach is reduced to a purely thermal one. Finally, the thermal events are simulated using FEM and compared to the temperature measurements. The results have shown that our modeling approach including non-linear properties of silicon can be used to investigate the thermal transients in SPS devices with high accuracy.

System level modeling of smart power switches using SystemC-AMS for digital protection concept verification

This paper presents a method for the compact modeling, simulation and experimental verification of digital protection functions of smart power switches consisting of a digital controller and a power MOSFET with analog driving circuitry. We focus on short circuit events in an automotive environment where high power dissipation and thermal stress severely affect device reliability. For accurate temperature calculation, a non-linear thermal network including coupling between power transistor channels is used. A digital strategy for over current limitation, short circuit detection and over-temperature shutdown is modeled using SystemC-AMS and verified experimentally using a hardware-in-the-loop system.

Improved thermal management of low voltage power devices with optimized bond wire positions

Abstract This paper focuses on optimization of bond wire positions as a method to improve thermal management of power semiconductors. For this purpose, robustness of a new low-voltage MOSFET generation with an optimized multiple bond wire arrangement and device shape is compared to an older device design with lower number of bond wires. 2D electrical simulation is used to evaluate the lateral distribution of power dissipation due to the gate voltage de-biasing effect. 3D thermal finite element simulation and infrared thermography measurements are employed to analyze the corresponding surface temperature distribution. Finally, tests under extreme single pulse short-circuit conditions demonstrate the effectiveness of thermal management for improving robustness in automotive applications.

Validated electro-thermal simulations of two different power MOSFET technologies and implications on their robustness

Power MOSFETs integrated in modern Smart Power switches feature a substantial high current capability due to the very low value of their transconductance coefficient K. In this paper we demonstrate that the trend related to the increasing current capability implies a reduced thermal stability range which may lead to less robust devices. Electro-thermal simulations of two test chips featuring two different technologies show that the higher the value of K, the less stable the device thermal behavior. Simulation results have been validated by means of temperature measurements performed using an integrated temperature sensor.

Design of a test chip with small embedded temperature sensor structures realized in a common-drain power trench technology

A test chip with the purpose of thermal monitoring and analysis is implemented in a common-drain smart power trench MOSFET technology. For accurate evaluation of the junction temperature, small embedded sensor structures are introduced. One sensor is a bipolar transistor structure based on the linear temperature dependence of the base-emitter voltage. An existing solution is modified in order to fit small embedded NPN devices into the MOSFET cell array. The second one is a resistive sensor implemented in the p-doped bulk silicon mesa of the trench power MOSFET technology, offering substantial design benefits. Variations of the sensor resistance caused by electric field effects are explained and characterized. The described sensor structures are integrated as close as possible to the active heat-generation area of the MOSFET, thus providing accurate junction temperature measurements without adversely affecting MOSFET temperature distribution. Accuracy of the described test structures is verified by calibrated transient infrared thermography, taking into account temperature gradients between junction and chip surface caused by thick metallization layers. A special test chip variant with different compositions of top layers is presented for the purpose of verifying the introduced sensor concepts.